Buffer device, method and apparatus for controlling access to internal memory

An apparatus for controlling data access to an internal memory, comprising:

• a controller coupled to a central processing unit to receive a data access signal;
• the data access signal containing a data access command and a destination address corresponding to a destination storage location in a memory module of the internal memory;
• the controller being configured to detect whether the destination address is within a predefined address space and generate a security access signal when the destination address is within the predefined address space;
• and
• a data interface coupled between the central processing unit and the memory module of the internal memory and coupled to the controller to exchange data between the central processing unit and the memory module of the internal memory under the control of the controller;
• the data interface being configured, in response to the security access signal, to obtain data to be exchanged from one of the central processing unit and the memory module of the internal memory, compare the data to be exchanged with reference data, and determine whether or not to restrict transferring of the data to be exchanged to the other of the central processing unit and the memory module of the internal memory;
• wherein the controller is integrated in a registering clock driver and the registering clock driver is configured to provide the security access signal to the data interface via a data buffer control bus.

An method for controlling data access to an internal memory, comprising:

• receiving via a central buffer module a data access signal;
• the data access signal containing a data access command and a destination address corresponding to a destination storage location in a memory module of the internal memory;
• detecting via the central buffer module whether the destination address is within a predefined address space, and generating via the central buffer module a security access signal when the destination address is within the predefined address space;
• and
• obtaining via a data buffer module in communication with the central buffer module data to be exchanged from one of a central processing unit and the memory module of the internal memory and comparing via the data buffer module the data to be exchanged with reference data in response of the security access signal, wherein the reference data is stored within the data buffer module;
• and
• determining via the data buffer module whether or not to restrict transferring of the data to be exchanged to the other of the central processing unit and the memory module of the internal memory;
• wherein the central buffer module is integrated in a registering clock driver and the registering clock driver is configured to provide the security access signal to the data buffer module via a data buffer control bus.