Metal oxide semiconductor cell device architecture with mixed diffusion break isolation trenches

A standard cell integrated circuit, comprising:

• a plurality of p-type metal oxide semiconductor (MOS) (pMOS) transistors in a pMOS region of the standard cell integrated circuit, the pMOS region extending between a first cell edge and a second cell edge opposite the first cell edge;
• a plurality of n-type MOS (nMOS) transistors in an nMOS region of the standard cell integrated circuit, the nMOS region extending between the first cell edge and the second cell edge,
• a first means for isolating diffusion regions located in an interior region between the first cell edge and the second cell edge and extending across the pMOS region and the nMOS region, the first means for isolating diffusion regions being configured to separate the pMOS region into pMOS subregions and the nMOS region into nMOS subregions, a width of the first means for isolating diffusion regions being approximately g;
• a second means for isolating diffusion regions extending at the first cell edge, a width of the second means for isolating diffusion regions being approximately p/2, p being greater than g;
• and
• a third means for isolating diffusion regions extending at the second cell edge, a width of the third means for isolating diffusion regions being approximately p/2.

A standard cell integrated circuit, comprising:

• a plurality of p-type metal oxide semiconductor (MOS) (pMOS) transistors in a pMOS region of the standard cell integrated circuit, the pMOS region extending between a first cell edge and a second cell edge opposite the first cell edge;
• a plurality of n-type MOS (nMOS) transistors in an nMOS region of the standard cell integrated circuit, the nMOS region extending between the first cell edge and the second cell edge,
• wherein the standard cell integrated circuit includes:
• means for providing at least one diffusion break located in an interior region between the first cell edge and the second cell edge and extending across the pMOS region and the nMOS region to separate the pMOS region into pMOS subregions and the nMOS region into nMOS subregions;
• means for providing a first diffusion break portion extending at the first cell edge, the means for providing the first diffusion break portion having a greater depth than the means for providing the at least one diffusion break;
• and
• means for providing a second diffusion break portion extending at the second cell edge, the means for providing the second diffusion break portion having a greater depth than the means for providing the at least one diffusion break.

An operating method of a standard cell integrated circuit, comprising:

• operating a plurality of p-type metal oxide semiconductor (MOS) (pMOS) transistors in a pMOS region of the standard cell integrated circuit, the pMOS region extending between a first cell edge and a second cell edge opposite the first cell edge;
• operating a plurality of n-type MOS (nMOS) transistors in an nMOS region of the standard cell integrated circuit, the nMOS region extending between the first cell edge and the second cell edge,
• wherein the standard cell integrated circuit includes:
• at least one single diffusion break located in an interior region between the first cell edge and the second cell edge and extending across the pMOS region and the nMOS region to separate the pMOS region into pMOS subregions and the nMOS region into nMOS subregions;
• a first double diffusion break portion extending at the first cell edge;
• and
• a second double diffusion break portion extending at the second cell edge.