US 9,824,974 B2Granted

Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies

AssigneeInvensas Corporation

InventorsGuilian Gao, Cyprian Emeka Uzoh, Charles G. Woychik, Hong Shen, Arkalgud R. Sitaram, Liang Wang, Akash Agrawal, Rajesh Katkar

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Abstract

Die (110) and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer (120) or some other structure (e.g. another integrated circuit) and are covered by an encapsulant (160). Then the interposer is thinned from below. Before encapsulation, a layer (410) more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.

Claims20

Dependent claims

An assembly comprising:

a first structure comprising first circuitry comprising one or more first contact pads at a top of the first structure;
one or more modules attached to a top surface of the first structure and electrically connected to at least one first contact pad, at least one module comprising at least one semiconductor integrated circuit;
a first layer formed on the top surface of the first structure;
and
a second layer overlying the first layer, wherein the second layer has a lower room-temperature elastic modulus than the first layer;
wherein at least one of the following is true:
(a) the first layer is inorganic;
(b) the first layer is a material different from any material found at an interface between the first structure and at least one of the one or more modules;
(c) the first layer covers all of that portion of said top surface which is not occupied by the one or more modules;
(d) the one or more modules comprise one or more first modules, the assembly comprising underfill between the first structure and each first module, the underfill extending laterally beyond each first module, and the first layer covers all of that portion of said top surface which is not occupied by the one or more modules and not covered by the underfill;
wherein:
the first structure comprises a first semiconductor substrate supporting the first circuitry;
in at least one of the one or more modules, at least one semiconductor integrated circuit comprises a second semiconductor substrate supporting the semiconductor integrated circuit;
and
the first semiconductor substrate is based on a different semiconductor than the second semiconductor substrate.

12 more elements

An assembly comprising:

a first structure comprising first circuitry comprising one or more first contact pads at a top of the first structure;
one or more modules attached to a top surface of the first structure and electrically connected to at least one first contact pad, at least one module comprising at least one semiconductor integrated circuit;
a first layer formed on the top surface of the first structure;
and
a second layer overlying the first layer, wherein the second layer has a lower room-temperature elastic modulus than the first layer;
wherein at least one of the following is true:
(a) the first layer is inorganic;
(b) the first layer is a material different from any material found at an interface between the first structure and at least one of the one or more modules;
(c) the first layer covers all of that portion of said top surface which is not occupied by the one or more modules;
(d) the one or more modules comprise one or more first modules, the assembly comprising underfill between the first structure and each first module, the underfill extending laterally beyond each first module, and the first layer covers all of that portion of said top surface which is not occupied by the one or more modules and not covered by the underfill;
wherein the first structure is an interposer, and the first circuitry further comprises one or more second contact pads at a bottom of the interposer;
wherein for a coefficient of thermal expansion (CTE) in an XY plane extending along the interposer, the XY CTE of the interposer is closer to the XY CTE of the first layer than to the XY CTE of the second layer.

9 more elements

An assembly comprising:

a first structure comprising first circuitry comprising one or more first contact pads at a top of the first structure;
one or more modules attached to a top surface of the first structure and electrically connected to at least one first contact pad, at least one module comprising at least one semiconductor integrated circuit;
a first layer formed on the top surface of the first structure;
and
a second layer overlying the first layer, wherein the second layer has a lower room-temperature elastic modulus than the first layer;
wherein at least one of the following is true:
(a) the first layer is inorganic;
(b) the first layer is a material different from any material found at an interface between the first structure and at least one of the one or more modules;
(c) the first layer covers all of that portion of said top surface which is not occupied by the one or more modules;
(d) the one or more modules comprise one or more first modules, the assembly comprising underfill between the first structure and each first module, the underfill extending laterally beyond each first module, and the first layer covers all of that portion of said top surface which is not occupied by the one or more modules and not covered by the underfill;
wherein the first structure is an interposer, and the first circuitry further comprises one or more second contact pads at a bottom of the interposer;
wherein for a coefficient of thermal expansion (CTE) in an XY plane extending along the interposer, the XY CTE of the first layer is at least 10% of, and at most three times, the XY CTE of the interposer.

9 more elements

An assembly comprising:

a first structure comprising first circuitry comprising one or more first contact pads at a top of the first structure;
one or more modules attached to a top surface of the first structure and electrically connected to at least one first contact pad, at least one module comprising at least one semiconductor integrated circuit;
a first layer formed on the top surface of the first structure;
and
a second layer overlying the first layer, wherein the second layer has a lower room-temperature elastic modulus than the first layer;
wherein at least one of the following is true:
(a) the first layer is inorganic;
(b) the first layer is a material different from any material found at an interface between the first structure and at least one of the one or more modules;
(c) the first layer covers all of that portion of said top surface which is not occupied by the one or more modules;
(d) the one or more modules comprise one or more first modules, the assembly comprising underfill between the first structure and each first module, the underfill extending laterally beyond each first module, and the first layer covers all of that portion of said top surface which is not occupied by the one or more modules and not covered by the underfill;
wherein the first structure is an interposer, and the first circuitry further comprises one or more second contact pads at a bottom of the interposer;
wherein the interposer comprises a substrate supporting the first circuitry;
and
for a coefficient of thermal expansion (CTE) in an XY plane extending along the interposer, the XY CTE of the substrate is closer to the XY CTE of the first layer than to the XY CTE of the second layer.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/364,534Filed 30 Nov 2016 · division
Priority: 4 Dec 2014
Published: US 2017/0084539 A123 Mar 2017
Granted: 21 Nov 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification31 codes

H10W 70/611
Insulating or insulated package substrates; Interposers; Redistribution layers: for connecting multiple chips together
H10P 72/74
For supporting or gripping: using temporarily an auxiliary support
H10W 70/095
Of insulating or insulated package substrates, or of interposers, or of redistribution layers: of vias therein
H10W 70/635
Vias, e.g. via plugs: through-vias

Family

Application62/087,361Us provisional application · filed 4 Dec 2014
Application14/704,714Parent of this division · filed 5 May 2015
US 2017/0084539 A1Pre-grant publication · published 23 Mar 2017
US 9,548,273 B2Parent of this division
US 2016/0163650 A1Published application
US 9,824,974 B2This patent

From the US filing history. Foreign family members aren’t listed.