Packaging solutions for devices and systems comprising lateral GaN power transistors

A method of fabricating a semiconductor device structure comprising an assembly of:

• a lateral GaN power transistor fabricated on a semiconductor substrate (GaN die) and packaging components comprising first and second leadframe layers for encapsulation within a package body, the method comprising:
• providing the GaN die comprising a front surface comprising source, drain and gate contact areas for the lateral GaN power transistor and a back surface for die-attach;
• providing a first leadframe layer and a second leadframe layer;
• the first leadframe layer being patterned to provide source, drain and gate portions, the source portion comprising an external source pad and a plurality of source fingers extending laterally from the source pad, the drain portion comprising an external drain pad and a plurality of drain fingers extending laterally from the drain pad, to provide source, drain and gate contact areas of the source, gate and drain portions corresponding to the source, drain and gate contact areas on the front surface of the GaN die;
• the second leadframe layer providing a thermal pad and die-attach area for the back surface of the GaN die,
• at least one of the first and second leadframe layers comprising a source clip portion which extends laterally of the die attach area of the second leadframe layer for vertical interconnection with the source portion of the first leadframe layer;
• attaching the back surface of the GaN die to the die-attach area of the second leadframe layer with a layer electrically and thermally conductive material;
• providing low inductance metal bump or metal post connections for source, drain and gate contact areas of the GaN die, and providing a layer of electrically and thermally conductive attachment material for any other surfaces to be electrically interconnected;
• mutually positioning the first and second leadframes to align respective source, drain and gate contacts thereof, with at least one of bump connections, post connections and attachment material therebetween;
• processing the respective bump connections, post connections and the attachment material to vertically attach, and thermally and electrically interconnect the source, drain and gate contact areas of the GaN die and respective source, drain and gate portions of the first copper leadframe layer;
• and
• providing a package body comprising an over-molding of encapsulation, exposing the thermal pad of second copper leadframe layer and exposing the external contact pads for the source, drain and gate of the lateral GaN transistor.