Partially depopulated interconnection arrays for packaged semiconductor devices and printed circuit boards
AssigneeLattice Semiconductor Corporation
InventorBan Pak Wong
Life of this patent
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AssigneeLattice Semiconductor Corporation
InventorBan Pak Wong
Estimating the term…
In one embodiment, a ball grid array (BGA) of a packaged semiconductor device and a corresponding landing pad array of a printed circuit board each have a layout defined by an interconnection array having (i) an inner sub-array of locations having connectors arranged in rows and columns separated by a specified pitch and (ii) an outer rectangular ring of locations having connectors arranged in rows and columns separated by the specified pitch. The outer rectangular ring is separated from the inner sub-array by a depopulated rectangular ring having a width of at least twice the specified pitch, wherein the depopulated rectangular ring has no connectors. The outer rectangular ring has empty locations having no connectors. Some of those empty locations define depopulated sets that divide the outer rectangular ring into a number of different contiguous sets of locations having connectors that enable pin escape for connectors of the device's BGA.
An article of manufacture comprising:
An article of manufacture comprising:
A method of assigning connectors in a semiconductor package to specified usages, comprising:
Dependencies are inferred from the claim text.