Ferroelectric memory cell without a plate line

A ferroelectric static random access memory (FeSRAM) cell, capable of operating under a static random access memory (SRAM) phase and a ferroelectric capacitor programming phase, comprising:

• first and second cross-coupled inverters connected between a power supply voltage signal and a ground reference voltage signal and holding a data signal represented in a complementary manner in first and second common data terminals;
• first and second select transistors coupled respectively to the first and second common data terminals of the cross-coupled inverters;
• and
• first, second, third and fourth ferroelectric capacitors, wherein, during the SRAM phase, the first and second ferroelectric capacitors couple the first common data terminal to the power supply voltage signal and the ground reference voltage signal, respectively, and wherein the third and the fourth ferroelectric capacitors couple the second common data terminal to the power supply voltage signal and the ground reference voltage signal, respectively.