Set associative cache memory with heterogeneous replacement policy

A method for operating a set associative cache memory having an array of storage elements arranged as M sets by N ways and an allocation unit that allocates the storage elements of the array in response to memory accesses that miss in the cache memory, wherein each of the memory accesses selects a set of the M sets, the method comprising:

• storing, for each parcel of a plurality of parcels, a parcel specifier that specifies:
• a subset of ways of the N ways that are included in the parcel, wherein the subsets of ways of parcels associated with a selected set are mutually exclusive;
• and
• a replacement scheme associated with the parcel from among a plurality of predetermined replacement schemes;
• for each memory access of the memory accesses:
• selecting the parcel specifier of a parcel of the plurality of parcels in response to the memory access;
• and
• using the replacement scheme associated with the parcel to allocate into the subset of ways of the N ways of the selected set that are included in the parcel;
• wherein each of the memory accesses has an associated memory access type (MAT) of a plurality of predetermined MATs;
• wherein the parcel specifier further associates one or more of the plurality of predetermined MATs with the parcel;
• and
• wherein said selecting the parcel specifier comprises selecting the parcel specifier of a parcel of the plurality of parcels based on the MAT of the memory access;
• wherein each of the memory accesses has an associated memory access type (MAT) of a plurality of predetermined MATs;
• wherein the parcel specifier further associates one or more of the plurality of predetermined MATs with the parcel;
• wherein the allocation unit selects the parcel specifier of a parcel of the plurality of parcels based on the MAT of the memory access;
• and
• wherein the plurality of predetermined MATs includes at least three from the following list:
• a memory access generated by a hardware prefetcher of the processor;
• a memory access generated by a floating point instruction;
• a memory access generated by a fused microinstruction;
• a memory access generated by a media instruction;
• a memory access generated by an instruction that modifies a memory address;
• a memory access generated by a software prefetch instruction;
• a memory access that loads an architectural descriptor;
• a memory access generated by an instruction that specifies non-temporal data;
• a memory access generated by an instruction that performs no alignment checks;
• a memory access generated by a supervisor privilege level instruction;
• a memory access generated by a zero extend instruction;
• a memory access generated by a masked move instruction;
• a memory access generated by a stack push instruction;
• and
• a memory access generated by a hardware tablewalk engine of the processor.

A set associative cache memory, comprising:

• an array of storage elements arranged as M sets by N ways;
• an allocation unit that allocates the storage elements of the array in response to memory accesses that miss in the cache memory, wherein each of the memory accesses selects a set of the M sets;
• and
• wherein the allocation unit uses a first replacement scheme when allocating into a first subset of the N ways of the selected set and a second replacement scheme when allocating into a second subset of the N ways of the selected set;
• wherein the first and second replacement schemes are different;
• wherein each of the memory accesses has an associated memory access type (MAT) of a plurality of predetermined MATs;
• wherein the MAT associated with the memory access is an input to the first replacement scheme used by the allocation unit when allocating into the first subset of the N ways of the selected set;
• and
• wherein the plurality of predetermined MATs includes at least three from the following list:
• a memory access generated by a hardware prefetcher of the processor;
• a memory access generated by a floating point instruction;
• a memory access generated by a fused microinstruction;
• a memory access generated by a media instruction;
• a memory access generated by an instruction that modifies a memory address;
• a memory access generated by a software prefetch instruction;
• a memory access that loads an architectural descriptor;
• a memory access generated by an instruction that specifies non-temporal data;
• a memory access generated by an instruction that performs no alignment checks;
• a memory access generated by a supervisor privilege level instruction;
• a memory access generated by a zero extend instruction;
• a memory access generated by a masked move instruction;
• a memory access generated by a stack push instruction;
• and
• a memory access generated by a hardware tablewalk engine of the processor.

A set associative cache memory, comprising:

• an array of storage elements arranged as M sets by N ways, wherein each set of the M sets includes associated replacement bits;
• an allocation unit that allocates the storage elements of the array in response to memory accesses that miss in the cache memory, wherein each of the memory accesses selects a set of the M sets;
• wherein the allocation unit uses a first subset of the replacement bits when allocating into a first subset of the N ways of the selected set and a second subset of the replacement bits when allocating into a second subset of the N ways of the selected set;
• wherein the first and second subsets of the replacement bits are mutually exclusive;
• wherein each of the memory accesses has an associated memory access type (MAT) of a plurality of predetermined MATs;
• wherein the allocation unit uses the MAT associated with the memory access to determine whether to use the first subset of the replacement bits to allocate into the first subset of the N ways of the selected set or to use the second subset of the replacement bits to allocate into the second subset of the N ways of the selected set;
• and
• wherein the plurality of predetermined MATs includes at least three from the following list:
• a memory access generated by a hardware prefetcher of the processor;
• a memory access generated by a floating point instruction;
• a memory access generated by a fused microinstruction;
• a memory access generated by a media instruction;
• a memory access generated by an instruction that modifies a memory address;
• a memory access generated by a software prefetch instruction;
• a memory access that loads an architectural descriptor;
• a memory access generated by an instruction that specifies non-temporal data;
• a memory access generated by an instruction that performs no alignment checks;
• a memory access generated by a supervisor privilege level instruction;
• a memory access generated by a zero extend instruction;
• a memory access generated by a masked move instruction;
• a memory access generated by a stack push instruction;
• and
• a memory access generated by a hardware tablewalk engine of the processor.