Back to results
US 9,807,417 B2Granted
Image processor
AssigneeMegaChips Corporation
InventorAkira Okamoto
Life of this patent
Estimating the term…
Abstract
The codec processor includes an SRAM that holds a reference image read from an image storage, and a motion search unit that performs motion search on the basis of a reference image held in the SRAM to generate a prediction block for a target block in an input image. The SRAM holds a reference image having a horizontally equivalent number of pixels to a horizontal number of pixels of the input image and a number of pixels vertically larger than or equal to a vertical motion search range.
Claims13
An image processor comprising:
- a codec processor configured to code an input image;
- and
- an image storage accessible by the codec processor,
- the codec processor including circuitry including:
- a first memory being configured to hold a reference image from the image storage and a second memory configured to hold a plurality of local decoded blocks.
- the circuitry being configured to perform motion search based on the reference image in the first memory to generate a prediction block for a target block in the input image,
- the first memory being further configured to hold the reference image having a horizontally equivalent number of pixels to a horizontal number of pixels of the input image and a number of pixels vertically larger than or equal to a vertical motion search range,
- the circuitry being further configured to:
- generate a prediction error based on the target block and the prediction block,
- reconstitute the target block based on the prediction error and the prediction block to generate a local decoded block,
- sequentially generate N local decoded blocks corresponding to N target blocks aligned row-wise in the input image, where N is an integer greater than one,
- write the N local decoded blocks in row-wise alignment to the second memory, and
- write the N local decoded blocks in the second memory to the image storage by burst transfer in a unit of a row across the N local decoded blocks.
10 more elements
An image processor comprising:
- a codec processor;
- a display processor configured to process image data to display an image on a display;
- and
- an image storage accessible by the codec processor and the display processor;
- the codec processor including circuitry including:
- a first memory configured to hold a reference image from the image storage and a second memory configured to hold a plurality of decoded blocks,
- the circuitry being configured to:
- perform motion search based on the reference image in the first memory to generate a prediction block for a target block;
- decode coded data to generate a prediction error;
- reconstitute an input image based on prediction block and the prediction error to generate a decoded block;
- sequentially generate N decoded blocks corresponding to N target blocks aligned row-wise in the input image, where N is an integer greater than one;
- write the N decoded blocks in row-wise alignment to the second memory:
- and
- write the N decoded blocks in the second memory to the image storage by burst transfer in a unit of a row across the N decoded blocks,
- the image storage being configured to transfer a decoded image therein to the display processor by burst transfer in the unit of the row, and
- the display processor being configured to display the image based on the decoded image from the image storage.
13 more elements
Dependencies are inferred from the claim text.