System and method for clock spur artifact correction

An integrated circuit, comprising:

• a digital-to-analog converter (DAC) comprising outputs coupled to a plurality of external signal paths, wherein the external signal paths comprise external switching stages coupled to a supply voltage input of an external amplifier;
• and
• a spur correction circuit coupled between a data input of the external amplifier and an input of the DAC, wherein:
• the spur correction circuit is configured for:
• obtaining a plurality of switching stage input signals generated in accordance with an input signal level of the external amplifier;
• and
• adjusting the plurality of switching stage input signals such that a clock spur harmonic artifact is reduced;
• the clock spur harmonic artifact comprises a first clock spur harmonic artifact generated, from a clock signal, in the plurality of external signal paths;
• and
• the adjusting the plurality of switching stage input signals comprises injecting a first continuous wave (CW) signal into the plurality of switching stage input signals in accordance with a previous amplitude of the first clock spur harmonic artifact, the injecting the first CW signal comprising:
• retrieving a first correction coefficient that was previously determined in accordance with the previous amplitude of the first clock spur harmonic artifact;
• and
• generating the first CW signal in accordance with the first correction coefficient,
• wherein the plurality of switching stage input signals comprises a basis signal and a phase-shifted replica of the basis signal, and wherein the basis signal comprises one of a pulse width modulated (PWM) signal or a digital signal corresponding to a PWM signal.