Fast direct feedback circuit for decision feedback equalization correction

Abstract

Embodiments include systems and methods for providing fast direct feedback to correct decision feedback equalization (DFE) in receiver circuits. Embodiments can provide direct feedback for DFE correction in a manner that is effective in high-speed data channels, while manifesting less latency, power consumption, and/or area than conventional DFE implementations. In some implementations, in each clock cycle (e.g., Tn), implementations can select (e.g., using a multiplexer) between a positive reference signal and a negative reference signal (e.g., both reference signals generated according to an inter-symbol interference magnitude for a data channel) according to a decision feedback signal from a previous clock cycle (Tn−1). The selected reference signal can be compared (e.g., in the same clock cycle Tn, using a comparator) with an input data signal to generated an updated decision feedback signal for a next clock cycle (e.g., Tn+1).

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