SAR analog-to-digital converter selective synchronization
AssigneeAnalog Devices Global
InventorsArvind Madan, Sandeep Monangi
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Abstract
A successive approximation routine (SAR) analog-to-digital converter integrated circuit can include multiple analog-to-digital converters (ADCs) sharing a reference voltage that can be perturbed by a capacitor array of a digital-to-analog converter (DAC) sampling the reference voltage, which can limit conversion accuracy. Synchronizing every bit trial across the ADCs can improve accuracy but can slow the conversion. Synchronizing a subset of at least one, but fewer than N, bit trials across ADCs can help obtain both speed and robustness. This selected subset can include bit trials corresponding to pro-defined critical events, such as those events for which a stable reference voltage node is particularly desirable.
Claims23
A successive approximation routine (SAR) multichannel analog-to-digital converter (ADC) integrated circuit device with multiple channels respectively including corresponding individual N-bit ADCs on the same integrated circuit to concurrently perform analog-to-digital conversions in parallel to concurrently convert respective analog signal samples into respective N-bit digital words using a reference voltage circuit shared by ADCs of different channels for bit trials, comprising:
- a synchronization circuit to synchronize between at least two channels a predefined subset of at least one, but fewer than N, of the bit trials across a selected subset of at least two of the ADCs in different ones of the multiple channels.
A successive approximation routine (SAR) multichannel analog-to-digital conversion (ADC) method of performing multiple N-bit ADCs of respective analog signal samples into respective N-bit digital words concurrently on the same integrated circuit using different channels including respective ADC circuits and sharing reference signal for use by the different channels during the concurrent analog-to-digital conversions, the method comprising:
- performing the concurrent analog-to-digital conversions in SAR bit trials;
- and
- synchronizing, between at least two channels, a predefined subset of at least one, but fewer than N, of the bit trials across a selected subset of at least two of the ADCs in different ones of multiple channels.
A successive approximation routine (SAR) multichannel analog-to-digital conversion (ADC) method of performing multiple N-bit ADCs of respective analog signal samples into respective N-bit digital words concurrently on the same integrated circuit using different channels including respective ADC circuits and sharing reference signal for use by the different channels during the concurrent analog-to-digital conversions the method comprising:
- performing the concurrent analog-to-digital conversions in SAR bit trials;
- and
- synchronizing, between all channels, a predefined subset of at least one, but fewer than N, of the bit trials across all of the different channels of ADC circuits on the same integrated circuit.
Dependencies are inferred from the claim text.