Phase lock loop

A phase lock loop (PLL), comprising:

• a phase frequency detector (PFD), for detecting a phase difference between a reference signal and a divided signal;
• a charge pump, coupled to the PFD, for providing a charge pump signal;
• a capacitor, coupled to the charge pump;
• an analog-to-digital convertor (ADC), coupled to the capacitor, for converting the charge pump signal to a first digital signal, and quantizing the first digital signal to a second digital signal;
• a noise canceller, coupled to the ADC, for forming a shaped noise signal according to the first and second digital signals, and eliminating the shaped noise signal at an output of the noise canceller to generate a noise cancelled signal, wherein the noise canceller performs noise shaping to a difference between the second digital signal and a scaled first digital signal to form the shaped noise signal;
• an accumulator, coupled to the noise canceller, for accumulating the noise cancelled signal to output an accumulated signal;
• a loop filter, coupled to the accumulator, for outputting a filtered signal in response to the accumulated signal;
• an oscillator, coupled to the loop filter, for providing an output oscillating signal in response to the filtered signal;
• a digital block, coupled to the ADC, for converting the second digital signal to a divider modulus control signal;
• and
• a frequency divider, coupled to the oscillator and the digital block, for dividing the frequency of the output oscillating signal according to the divider modulus control signal to generate the divided signal.