Switched-capacitor circuits in a PLL
AssigneeQUALCOMM Incorporated
InventorsMojtaba Sharifzadeh, Alireza Khalili, Mazhareddin Taghivand, Mohammad Emadi
Life of this patent
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Abstract
Various aspects of this disclosure describe switched-capacitor circuits in a PLL. Examples include routing current from a first current source through a capacitor to ground during a first clock phase, routing current from a second current source through the capacitor to ground during a second clock phase, and transferring charge on the capacitor to a loop filter capacitor during a third clock phase. The first current source may generate current responsive to UP error samples from a phase/frequency detector (PFD), and the second current source generates current responsive to DN error samples from the PFD.
Claims27
A circuit for transferring charge to a loop filter in a phase-locked loop (PLL), the circuit comprising:
- a first current source connected to a first terminal of a first switch;
- a second current source connected to a first terminal of a second switch;
- a first capacitor having a first terminal connected to a second terminal of the first switch and a second terminal connected to a second terminal of the second switch;
- a third switch connected from the first terminal of the first capacitor to ground;
- a fourth switch connected from the second terminal of the first capacitor to ground;
- and
- a fifth switch connected from the second terminal of the capacitor to a second capacitor in the loop filter in the PLL, the first switch and the fourth switch configured to be closed during a first clock phase, and the second switch, the third switch, and the fifth switch configured to be open during the first clock phase.
A circuit for transferring charge to a loop filter in a phase-locked loop (PLL), the circuit comprising:
- a first current source connected to a first terminal of a first switch;
- a second current source connected to a first terminal of a second switch;
- a first capacitor having a first terminal connected to a second terminal of the first switch and a second terminal connected to a second terminal of the second switch;
- a third switch connected from the first terminal of the first capacitor to ground;
- a fourth switch connected from the second terminal of the first capacitor to ground;
- and
- a fifth switch connected from the second terminal of the capacitor to a second capacitor in the loop filter in the PLL, the first switch and the fourth switch configured to be closed during a first clock phase, and the second switch, the third switch, and the fifth switch configured to be open during the first clock phase,
- wherein the first current source, the second current source, the first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the first capacitor comprise a unit cell, and the circuit further comprises a second unit cell and a third unit cell with a third capacitor and a fourth capacitor, respectively.
A charge pump in a phase-locked loop (PLL), the charge pump comprising:
- a first current source;
- a second current source;
- a capacitor;
- and
- a plurality of switches configured to:
- route current from the first current source through the capacitor to ground during a first clock phase;
- route current from the second current source through the capacitor to ground during a second clock phase;
- and
- transfer charge on the capacitor to a loop filter in the PLL during a third clock phase, the first clock phase, the second clock phase, and the third clock phase being different phases of a clock.
A device comprising:
- means for routing current from a first current source through a first capacitor to ground during a first clock phase;
- means for routing current from a second current source through the first capacitor to ground during a second clock phase;
- and
- means for transferring charge on the first capacitor to a second capacitor in a loop filter of a phase-locked loop (PLL) during a third clock phase, the first clock phase, the second clock phase, and the third clock phase being different phases of a clock.
A method for transferring charge to a loop filter in a phase-locked loop (PLL), the method comprising:
- interleaving a plurality of charge pump circuits over a plurality of clock phases, each of the plurality of charge pump circuits comprising:
- a first current source;
- a second current source;
- a capacitor;
- and
- a plurality of switches;
- routing current with at least some of the plurality of switches of a first charge pump circuit of the plurality of charge pump circuits from the first current source of the first charge pump circuit through the respective capacitor of the first charge pump circuit to ground during at least one of the clock phases;
- routing current with at least some of the plurality of switches of a second charge pump circuit of the plurality of charge pump circuits from the second current source of the second charge pump circuit through the respective capacitor of the second charge pump circuit to ground during the at least one of the clock phases;
- and
- transferring charge on the respective capacitor of a third charge pump circuit of the plurality of charge pump circuits to the loop filter in the PLL with at least some of the plurality of switches of the third charge pump circuit during the at least one of the clock phases.
Dependencies are inferred from the claim text.