High frequency delay lock loop systems
AssigneeInphi Corporation
InventorsGuojun Ren, James Gorecki, Karthik S. Gopalakrishnan
Life of this patent
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Abstract
The present invention is directed to signal processing system and electrical circuits. According to various embodiments, a DLL system includes a delay line provides multiple output signals associated with different clock phases. The delay line may be adjusted using a pair of bias voltages. A phase detector systems generates the bias voltages using the multiple output signals from the delay line. The multiple output signals include signals associated with the first phase, the last phase, and two adjacent phases. There are other embodiments as well.
Claims20
A method for operating a delay lock loop (DLL) system, the method comprising:
- receiving a square clock signal;
- maintaining an edge shape of the square clock signal;
- generating n output signals using a delay line and the square clock signal, the n output signals including a first phase signal and a last phase signal;
- determining an accumulated phase offset using the first phase signal and the last phase signal;
- determining a reference phase offset using two adjacent output signals of the n output signals;
- generating a correctional signal using at least the accumulated phase offset and the reference phase offset;
- generating a first bias voltage and a second bias voltage using at least the correction signal.
A method for operating a receiver system, the method comprising:
- receiving a reference clock signal;
- performing phase interpolation on the reference clock signal to generate a corrected clock signal;
- generating n output signals based on the corrected clock signal, the n output signals including a first phase signal and a last phase signal;
- determining an accumulated phase offset using the first phase signal and the last phase signal;
- determining a reference phase offset using two adjacent output signals of the n output signals;
- generating a correctional signal using at least the accumulated phase offset and the reference phase offset;
- generating a first bias voltage and a second bias voltage using at least the correction signal;
- and
- generating a plurality of delayed signals using at least the corrected clock signal and the first bias voltage.
A method for operating a delay-lock loop (DLL) system, the method comprising:
- receiving a clock signal;
- generating n output signals using a delay line and the clock signal, the n output signals including a first phase signal and a last phase signal;
- determining an accumulated phase offset using the first phase signal and the last phase signal;
- filtering the accumulated phase offset to provide a first filtered offset;
- determining a reference phase offset using two adjacent output signals of the n output signals;
- filtering the reference phase offset to provide a second filtered offset;
- generating a correction signal using at least the first filtered offset and the second filtered offset;
- and
- generating a first bias voltage and a second bias voltage using at least the correction signal.
Dependencies are inferred from the claim text.