Back to results
US 9,806,721 B2Granted
Multiple data rate counter, data converter including the same, and image sensor including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsKyung-min Kim, Kyoung-min Koh, Yoon-seok Han
Life of this patent
Estimating the term…
Abstract
A counter includes a buffer unit and a ripple counter. The buffer unit generates at least one least significant signal of a count by buffering at least one clock signal until a termination time point. The ripple counter generates at least one most significant signal of the count by sequentially toggling in response to at least one of the least significant signal. The counter performs multiple data rate counting with enhanced operation speed and reduced power consumption.
Claims19
An image sensor comprising:
- a pixel array including a plurality of pixels configured to generate image signals;
- a driver/address decoder configured to control an operation of the pixel array;
- a correlated double sampling (CDS) circuit configured to perform an analog double sampling based on the image signals;
- a comparator configured to generate a comparison signal based on the image signals and a reference signal;
- and
- a counter configured to receive the comparison signal from the comparator and configured to generate a digital signal, the counter including:
- a plurality of low-level bit latches configured to latch a plurality of low-level bit signals of the digital signal that include a least significant bit (LSB) signal;
- and
- a plurality of high-level bit counting units configured to generate at least one high-level bit signal of the digital signal that includes a most significant bit (MSB) signal,
- wherein the plurality of high-level bit counting units are a ripple counter, the plurality of low-level bit signals of the digital signal include a first signal, a second signal, and a third signal that are represented in a gray code, and
- wherein the comparison signal indicates a termination time point of a counting operation of the counter.
8 more elements
An image sensor comprising:
- a pixel array including a plurality of pixels configured to generate image signals;
- a driver/ address decoder configured to control an operation of the pixel array;
- a correlated double sampling (CDS) circuit configured to perform an analog double sampling based on the image signals from the pixel array;
- a comparator configured to generate a comparison signal based on the image signals and a reference signal;
- and
- a multiple data rate (MDR) counter configured to receive the comparison signal from the comparator, configured to generate a digital signal and configured to count at least two times every period of a clock signal, the MDR counter including:
- a plurality of buffers configured to latch a plurality of low-level bit signals including a least significant bit (LSB) signal;
- and
- a ripple counter configured to count at least one high-level bit signal of the MDR counter, the at least one high-level bit signal including a most significant bit (MSB) signal, wherein
- the plurality of low-level bit signals are represented in a gray code,
- the comparison signal indicates a termination time point of a counting operation of the counter, and
- the at least one high-level bit signal sequentially toggles.
9 more elements
A counter for generating a digital signal including a plurality of low-level bit signals and a plurality of high-level bit signals, the counter comprising:
- a first buffer configured to latch a first signal among the plurality of low-level bit signals, the first buffer configured to buffer a first clock signal;
- a second buffer configured to latch a second signal among the plurality of low-level bit signals, the second buffer configured to buffer a second clock signal;
- a third buffer configured to latch a third signal among the plurality of low-level bit signals, the third buffer configured to buffer a third clock signal;
- and
- a ripple counter configured to count the plurality of high-level bit signals including a most significant bit (MSB) signal, wherein
- the plurality of low-level bit signals include a least significant bit (LSB) signal,
- the first, second and third signals are three low-level bit signals represented in a gray code, the three low-level bit signals including the least significant bit (LSB) signal,
- the first clock signal has a different phase from the second clock signal, and
- the third clock signal has a different phase from the second clock signal.
6 more elements
Dependencies are inferred from the claim text.