Back to results
US 9,806,720 B1Granted
Compound semiconductor based inverter
AssigneeAnalog Devices Global
InventorsBilal Tarik Cavus, Ozgun Serttek, Mehmet Bati
Life of this patent
Estimating the term…
Abstract
An inverter based on a compound semiconductor uses a depletion mode transistor as the pull-up device, and a current source to bias the pull-up device. The current source is electrically coupled to a source terminal of the pull-up device. As a result, the current source continues to conduct current through the pull-up device, whether the inverter output is high or low, to ensure rapid response of the inverter.
Claims20
A compound semiconductor inverter circuit, comprising:
- a pull-down FET, integrated with a compound semiconductor substrate;
- a depletion mode pull-up FET, integrated with the compound semiconductor substrate;
- a bias current source, integrated with the compound semiconductor substrate, the bias current source electrically connected to a source terminal of the depletion mode pull-up FET to keep the depletion mode pull-up FET on by providing a bias current when the pull-down FET is off;
- and
- a voltage drop circuit, electrically coupled between the source terminal of the depletion mode pull-up FET and a gate terminal of the depletion mode pull-up FET, and electrically coupled to a drain terminal of the pull-down FET to maintain a source-gate bias voltage between the source and gate terminals of the depletion mode pull-up FET to keep the depletion mode pull-up FET on at least when the pull-down FET is turned on and sinking current through the voltage drop circuit.
2 more elements
A device, comprising:
- a circuit package with a plurality of attenuation input leads;
- a digital attenuator in the circuit package that receives an input signal and outputs an output signal that is an attenuated version of the input signal with an attenuation determined by a plurality of attenuation control signal inputs received by the digital attenuator;
- a plurality of compound semiconductor inverter circuits in the circuit package and integrated with a compound semiconductor substrate, each compound semiconductor inverter circuit of the plurality of compound semiconductor inverter circuits including:
- a pull-down FET, integrated with the compound semiconductor substrate;
- a depletion mode pull-up FET, integrated with the compound semiconductor substrate;
- a bias current source, integrated with the compound semiconductor substrate, the bias current source electrically connected to a source terminal of the depletion mode pull-up FET to keep the depletion mode pull-up FET on;
- and
- a voltage drop circuit, electrically coupled between the source terminal of the depletion mode pull-up FET and a gate terminal of the depletion mode pull-up FET, and electrically coupled to a drain terminal of the pull-down FET to maintain a source-gate bias voltage between the source and gate terminals of the depletion mode FET to keep the depletion mode pull-up FET on at least when the pull-down FET is turned on and sinking current through the voltage drop circuit,
- wherein the plurality of compound semiconductor inverter circuits have inverter input nodes electrically coupled to the plurality of attenuation input leads, and the plurality of compound semiconductor inverter circuits have inverter output nodes electrically coupled to the plurality of attenuation control signal inputs.
6 more elements
A method of inverting an input signal using a compound semiconductor inverter circuit including a depletion mode pull-up FET and a pull-down FET, the method comprising:
- responsive to an inverter input node receiving a logic high input voltage, turning on a pull-down FET and providing a logic low output voltage equal to a magnitude of a turn-on threshold voltage of the depletion mode pull-up FET while biasing the depletion mode pull-up FET on via a pull-up FET bias current and a pull-up FET gate-source bias circuit;
- and
- responsive to the inverter input node receiving a logic low input voltage, turning off the pull-down FET and providing a logic high output voltage equal to an upper supply voltage applied to the inverter circuit while continuing to provide the pull-up FET bias current when the pull-down FET is off.
Dependencies are inferred from the claim text.