Circuits and methods for DFE with reduced area and power consumption

A combined slicer and summer circuit, comprising:

• differential output lines connected to a plurality of differential currents to be summed, the differential currents forming continuous-time infinite impulse response (IIR) filter signals provided as feedback in a decision feedback equalizer (DFE) and including an input signal produced by a linear transconductor and a tap signal;
• a resettable current-comparator load directly coupled to the differential output lines, the current-comparator load configured to directly receive summed differential currents from the differential output lines;
• and
• a passgate sample-and-hold that receives data input signals and produces a constant output during an evaluation phase, comprising a resistor to degenerate the input signals and a switch triggered by a clock signal to hold the data input signal during an evaluation phase and to reduce frequency-dependent loss,
• wherein the resettable current-comparator load resets a differential voltage of the differential output lines to zero during a first phase of the clock signal and discharges parasitic capacitances of the output lines and further discharges the plurality of different currents onto the differential output lines during a second phase of the clock signal, such that depending on a sign of the summed differential currents, either a positive or negative differential voltage develops between the differential output lines,
• wherein a slicer turns on when an output common-mode falls below a threshold to latch a binary zero or one based on the positive or negative differential voltage, and
• wherein the passgate sample-and-hold is coupled to the linear transconductor to receive the input signal as switched by the clock signal to hold the input signal to the linear transconductor constant during the second phase of the clock signal.