Systems and methods for a low hold-time sequential input stage
AssigneeAltera Corporation
InventorsDana How, Herman Henry Schmit
Life of this patent
Estimating the term…
Abstract
Systems and methods for a low hold-time sequential input stage provide circuitry that includes a first latch element receiving a first input. The first latch element is connected to a first two-input multiplexer. The circuitry further includes a second latch element receiving a second input. The second latch element is connected to the first two-input multiplexer. The first input and the second input originate from different input cells of an input column that receive a same source signal.
Claims19
Circuitry for sequential input stages, the circuitry comprising:
- a first latch element receiving a first input, the first latch element connected to a first two-input multiplexer;
- a second latch element receiving a second input, the second latch element connected to the first two-input multiplexer;
- wherein the first input and the second input originate from different input cells of an input column that receive a same source signal, wherein the first input and the second input are configurable to receive either a same input value or different respective input values;
- and
- wherein, when the same input value is routed to the first input and the second input, a combination of the first latch element, the second latch element, and the first two-input multiplexer is configurable to collectively act as a Double-Edge-Triggered (DET) flip-flop and, when the different input values are routed to the first input and the second input, the combination of the first latch element, the second latch element, and the first two-input multiplexer is configurable to collectively not act as the Double-Edge-Triggered (DET) flip-flop.
A method of configuring an input stage circuit, the method comprising:
- configuring a first latch element to receive a first input, the first latch element connected to a first two-input multiplexer;
- configuring a second latch element to receive a second input, the second latch element connected to the first two-input multiplexer and to a second two-input multiplexer;
- configuring a third latch element to receive a third input, the third latch element connected to the second two-input multiplexer and a third two-input multiplexer;
- and
- configuring the first input and the second input to originate from different input cells of an input column that receive a same source signal;
- and
- configuring the different input cells of the first input and the second input to provide a same input value from the same source signal.
A processor-readable non-transitory medium storing processor-executable instructions for configuring an input stage circuit, the processor-executable instructions comprising:
- instructions executable by a processor to configure a first latch element to receive a first input, the first latch element connected to a first two-input multiplexer;
- instructions executable by the processor to configure a second latch element to receive a second input, the second latch element connected to the first two-input multiplexer and to a second two-input multiplexer;
- instructions executable by the processor to configure the first input and the second input to originate from different input cells of an input column that receive a same source signal;
- instructions executable by the processor to configure the different input cells of the first input and the second input to provide a same input value from the same source signal;
- and
- instructions executable by the processor to configure the first latch element, the second latch element, and the first two-input multiplexer to collectively act as a Double-Edge-Triggered (DET) flip-flop.
Dependencies are inferred from the claim text.