Integrated Circuit Devices Having Clock Gating Circuits Therein
AssigneeSamsung Electronics Co., Ltd.
InventorByung-jo Kim
Life of this patent
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Abstract
An integrated circuit device includes a clock gating circuit, which is configured to generate a first plurality of clocks in response to a first reference clock at a first frequency and a plurality of operation enable signals. A plurality of functional circuits are provided, which are responsive to respective ones of the first plurality of clocks. The plurality of functional circuits is configured to generate respective ones of the plurality of operation enable signals, with each of the plurality of operation enable signals having a first logic state that enables a respective clock within said clock gating circuit and a second logic state that disables the respective clock within said clock gating circuit.
Claims16
An integrated circuit device, comprising:
- a clock gating circuit configured to generate a first plurality of clocks in response to a first reference clock at a first frequency and a plurality of operation enable signals;
- and
- a plurality of functional circuits responsive to respective ones of the first plurality of clocks, said plurality of functional circuits configured to generate respective ones of the plurality of operation enable signals, with each of the plurality of operation enable signals having a first logic state that enables a respective clock within said clock gating circuit and a second logic state that disables the respective clock within said clock gating circuit;
- wherein said clock gating circuit is further responsive to a register enable signal and an address designating one of said plurality of functional circuits;
- wherein the register enable signal has active and inactive logic states;
- and
- wherein an overlapping combination of an active register enable signal and an address designating a first of said plurality of functional circuits causes said clock gating circuit to provide the first of said plurality of functional circuits with a respective clock.
A semiconductor device comprising:
- a plurality of function blocks configured to perform different functions;
- a clock generator configured to generate a reference clock;
- and
- a clock gating unit configured to generate a plurality of clocks respectively corresponding to the plurality of function blocks, based on the reference clock, respectively supply the plurality of clocks, to the plurality of function blocks, and perform gating on the plurality of clocks, based on, a state of an enable signal and an address received by said clock gating unit, said enable signal having active and inactive states and said address designating a corresponding one of the plurality of function blocks.
A semiconductor device comprising:
- a first function block including at least one first register that operates, based on a first clock;
- a second function block including at east one second register that operates based on a second clock;
- an interface unit configured to receive data and an address from an external device and transmit the data to one of the first and second registers that corresponds to the address;
- and
- a clock gating unit configured to perform gating on a reference clock to generate the first clock and the second clock, supply the first clock to the first function block through a first line, and supply the second clock to the second function block through a second line, said clock gating unit responsive to address information generated by said interface unit.
Dependencies are inferred from the claim text.