System and method for signal amplification using a resistance network

An amplification device, comprising:

• a resistance network coupled between a first output of the amplification device and a second output of the amplification device,
• a first transistor having a control terminal coupled to a first input node of the amplification device and a first load path terminal coupled to the resistance network at a first node;
• a second transistor having a control terminal coupled to a second input node of the amplification device and a first load path terminal coupled to the resistance network at a second node, wherein at least one of the first input node and the second input node is configured to be coupled to a capacitive sensor;
• a first inverting amplifier comprising an input coupled to a second load path terminal of the first transistor and an output coupled to a first output node of the amplification device;
• and
• a second inverting amplifier comprising an input coupled to a second load path terminal of the second transistor and an output coupled to a second output node of the amplification device;
• a first resistance coupled between a second control terminal of the first transistor and a third node of the resistance network;
• a second resistance coupled between the second control terminal of the first transistor and the output of the first inverting amplifier;
• a third resistance coupled between a second control terminal of the second transistor and the third node of the resistance network;
• and
• a fourth resistance coupled between the second control terminal of the second transistor and the output of the second inverting amplifier;
• and wherein:
• a voltage gain of the amplification device is in accordance with a ratio of the second resistance divided by the first resistance, and
• a ratio of the fourth resistance divided by the third resistance is the same as the ratio of the second resistance divided by the first resistance.

A method for signal amplification, comprising:

• receiving, by a first control terminal of a first transistor, a first input signal from a capacitive sensor;
• receiving, by a first control terminal of a second transistor, a second input signal from the capacitive sensor;
• producing a first output signal, producing the first output signal comprising amplifying a first signal at a first load path terminal of the first transistor using a first inverting amplifier having an output coupled to a resistance network, and receiving, at a load path terminal of a third transistor comprised in the first inverting amplifier, the first signal from the first load path terminal of the first transistor;
• producing a second output signal, producing the second output signal comprising amplifying a second signal at a first load path terminal of the second transistor using a second inverting amplifier having an output coupled to the resistance network, the producing the second output signal further comprises receiving, at a load path terminal of a fourth transistor comprised in the second inverting amplifier, the second signal from the first load path terminal of the second transistor;
• and
• feeding back the first output signal and the second output signal to a second load path terminal of the first transistor and to a second load path terminal of the second transistor via the resistance network according to a pre-determined fraction, wherein
• the resistance network comprises a plurality of series connected resistors coupled between the output of the first inverting amplifier at a first node and the output of the second inverting amplifier at a second node,
• a second control terminal of the first transistor is selectably coupled to a third node of the resistance network between the first node and the second node, and
• a second control terminal of the second transistor is selectably coupled to a fourth node of the resistance network between the third node and the second node.

An amplifier system, comprising:

• a first transistor having a control terminal coupled to a first input node;
• a second transistor having a control terminal coupled to a second input node;
• a first inverting amplifier comprising a third transistor having a first load path terminal coupled to the first load path terminal of the first transistor;
• a first output node coupled to an output of the first inverting amplifier;
• a second inverting amplifier comprising a fourth transistor having a first load path terminal coupled to the first load path terminal of the second transistor;
• a second output node coupled to an output of the second inverting amplifier;
• and
• a switchable resistance network coupled between the output of the first inverting amplifier and the output of the second inverting amplifier, wherein the switchable resistance network is selectably coupled to a second load path terminal of the first transistor and to a second load path terminal of the second transistor.