High-linearity CMOS WiFi RF power amplifiers in wide range of burst signals

An RF power amplifier biasing circuit with a start ramp signal input, a main current source input, an auxiliary current source input, and a circuit output, the RF power amplifier biasing circuit comprising:

• a ramp-up capacitor connected to the auxiliary current source input;
• a ramp-up switch transistor connected to the start ramp signal input, the ramp-up switch transistor being selectively activated thereby to connect the auxiliary current source input to the ramp-up capacitor;
• a buffer stage with an input connected to the ramp-up capacitor and an output connected to the main current source input at a sum node;
• and
• a mirror transistor with a gate terminal corresponding to the circuit output and a drain terminal connected to the sum node and to the gate terminal.

An RF power amplifier biasing circuit with a biasing output and connectable to a band gap reference circuit with a first current output generating a first voltage level and a second current output generating a second voltage level, the circuit comprising:

• a switch having a first throw terminal connected to the first current output of the band gap reference circuit, a second throw terminal connected to the second current output of the band gap reference circuit, and a pole terminal, the switch selectively connecting the first throw terminal and the second throw terminal to the pole terminal in response to a switch enable input;
• an operational amplifier with a first differential input, a second differential input, and an operational amplifier output, the operational amplifier being powered by the band gap reference circuit;
• a ramping resistor-capacitor network connected to the first differential input of the operational amplifier, a ramping resistor of the ramping resistor-capacitor network being connected to the pole terminal of the switch;
• an output transistor connected to the output of the operational amplifier and having an output defining the biasing output;
• and
• a feedback resistor network connected to the output transistor and to the second differential input of the operational amplifier;
• wherein a voltage on the biasing output ramps from the first voltage level to the second voltage level in conjunction with the switch being selectively activated from connecting the first throw terminal and the pole terminal, to connecting the second throw terminal and the pole terminal.