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US 9,806,195 B2Granted
Method for fabricating transistor with thinned channel
AssigneeIntel Corporation
InventorsJustin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Brian S. Doyle, Jack T. Kavalieros, Amlan Majumdar, Matthew V. Metz, Marko Radosavljevic
Life of this patent
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Abstract
A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
Claims24
A mobile computing device, comprising:
- one or more electronic memories;
- and
- one or more processors coupled to the memories by a bus, wherein at least one of the processors includes at least one transistor further comprising:
- a semiconductor body disposed over a substrate, the semiconductor body having a first width, a second width, a length, and a height;
- a source region disposed within a first end of the semiconductor body having the first width and the height;
- a drain region disposed within a second end of the semiconductor body having the first width and the height, the second end opposite the first end;
- a channel region disposed only in a portion of the semiconductor body having the second width and the height and disposed between the source region and the drain region, wherein:
- the length of the semiconductor body runs from the source region through the channel region to the drain region;
- the second width is narrower than the first width;
- the height of the semiconductor body is taken from an interface of the substrate and the semiconductor body to a top surface of the semiconductor body opposite the substrate;
- and
- the first and second width are orthogonal to the length and the height;
- a gate stack disposed over the channel region, the gate stack having a distance between sidewalls of the gate stack equal to and in direct alignment with the length of the portion of the semiconductor body having the second width, wherein the gate stack comprises a gate dielectric layer and a gate electrode;
- and
- a pair of spacers adjacent to the sidewalls of the gate stack, wherein the pair of spacers are recessed into the semiconductor body.
12 more elements
A mobile computing device, comprising:
- one or more electronic memories;
- and
- one or more processors coupled to the memories by a bus, wherein at least one of the processors includes at least one transistor further comprising:
- a semiconductor body disposed above a substrate, the semiconductor body having a width, a length, a first height, and a second height;
- a source region disposed within a first end of the semiconductor body having the first height and the width;
- a drain region disposed within a second end of the semiconductor body, opposite the first, and having the first height and the width;
- a channel region disposed within a portion of the semiconductor body having the second height and the width between the source region and the drain region,
- wherein:
- the second height is shorter than the first height;
- the length of the semiconductor body runs from the source region through the channel region to the drain region;
- the first and second heights of the semiconductor body are from an interface of the semiconductor body and the substrate to a top surface of the semiconductor body;
- and
- the width is orthogonal to the length and the first and second heights;
- and
- a gate stack disposed above the channel region, the gate stack having a distance between sidewalls of the gate stack equal to, and in direct alignment with, the length of the portion of the semiconductor body having the second height, wherein the gate stack comprises a gate dielectric layer and a gate electrode.
12 more elements
Dependencies are inferred from the claim text.