High voltage drain extension on thin buried oxide SOI
AssigneeTexas Instruments Incorporated
InventorsMarie Denison, Philip L. Hower, Sameer Pendharkar
Life of this patent
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Abstract
An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) coupled to the handle wafer through a p-n junction, that is electrically isolated from the drain or body region. A process of forming an integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel).
Claims12
An integrated circuit, comprising:
- a silicon on insulator (SOI) substrate, including:
- a handle wafer, of semiconductor material having a first conductivity type;
- a buried oxide layer, of dielectric material, located on a top surface of said handle wafer;
- and
- an SOI film of semiconductor material, located on a top surface of said buried oxide layer;
- and
- an extended drain metal oxide semiconductor (MOS) transistor, including:
- a region located in said SOI film, said region extending from a top surface of the SOI film to said buried oxide layer and having an opposite conductivity type from said handle wafer;
- and
- a through substrate diode extending through said region, including:
- a through substrate via extending from a top surface of said SOI film through said buried oxide layer into said handle wafer;
- an electrically conductive via fill plug in said through substrate via, said via fill plug making electrical contact to said SOI film adjacent to said through substrate vias and to said handle wafer, wherein said via fill plug includes polysilicon of said first conductivity type;
- and
- a p-n junction adjacent to a boundary of said through substrate via, said p-n junction including a first p-n region in said SOI film extending from a top-surface of said SOI film to said buried oxide layer on at least two opposite sides of the through substrate via.
A process of forming an integrated circuit, comprising steps:
- providing an SOI substrate, said SOI substrate including:
- a handle wafer, of semiconductor material having a first conductivity type;
- a buried oxide layer, of dielectric material, formed on a top surface of said handle wafer;
- and
- an SOI film of semiconductor material, formed on a top surface of said buried oxide layer;
- and
- forming an extended drain metal oxide semiconductor (MOS) transistor, by a process including steps:
- forming a region located in said SOI film, so that said region extends from a top surface of the SOI film to the buried layer and has an opposite conductivity type from said handle wafer;
- and
- forming a through substrate diode in said region, by a process including steps:
- forming a through substrate via extending from a top surface of said SOI film through said region and said buried oxide layer into said handle wafer;
- forming an electrically conductive via fill plug in said through substrate via, said via fill plug making electrical contact to said handle wafer, wherein said via fill plug includes polysilicon of said first conductivity type;
- and
- forming a p-n junction adjacent to a boundary of said through substrate via, said p-n junction including a first p-n junction region in said SOI film extending from a top-surface of said SOI film to said buried oxide layer on at least two opposite sides of the through substrate via.
Dependencies are inferred from the claim text.