Termination region architecture for vertical power transistors

An integrated circuit comprising:

• a semiconductor substrate of a first conductivity type;
• an epitaxial layer of the first conductivity type overlying the substrate, the epitaxial layer having a lighter dopant concentration than the substrate;
• a core region disposed into a surface of the epitaxial layer, the core region including an array of vertical transistor structures with terminal nodes electrically connected in parallel, the substrate serving as one of the terminal nodes of the vertical transistor structures, the core region having a plurality of sides aligned in parallel with edges of the integrated circuit;
• a termination region surrounding the core region;
• and
• a first termination structure having a portion overlying a portion of the termination region and disposed at or near a surface of the termination region;
• wherein a first edge of the first termination structure has at least one substantially linear portion parallel to a side of the core region, and at least one curved corner portion substantially following a second-order smooth curve with varying local radii of curvature.