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US 9,806,180 B2Granted
Forming a non-planar transistor having a quantum well channel
AssigneeIntel Corporation
InventorsChi On Chui, Prashant Majhi, Wilman Tsai, Jack T. Kavalieros
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Abstract
In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.
Claims12
An apparatus comprising:
- a substrate;
- a buried oxide layer formed directly on the substrate and between the substrate and a semiconductor fin;
- the semiconductor fin comprising a silicon on insulator core formed directly on the buried oxide layer, the semiconductor fin providing a channel region for a non-planar field effect transistor (FET);
- a first semiconductor layer comprising silicon germanium (SiGe) directly formed on and wrapped around the semiconductor fin, wherein the first semiconductor layer comprises a quantum well layer including a smaller bandgap than a bandgap of the semiconductor fin, the SiGe having a Ge concentration of at least approximately 10%;
- a second semiconductor layer comprising tensile strained silicon directly wrapped around and on the first semiconductor layer;
- and a dielectric layer adjacent the second semiconductor layer;
- wherein the first semiconductor layer provides a quantum well for holes;
- and wherein the second semiconductor layer provides a quantum well for electrons.
5 more elements
An apparatus comprising:
- a substrate;
- a buried oxide layer directly formed on the substrate;
- a semiconductor fin directly formed on the buried oxide layer, the semiconductor fin comprising a silicon on insulator core and providing a channel region for a non-planar field effect transistor (FET);
- a first semiconductor layer comprising silicon germanium (SiGe) directly formed on and wrapped around the semiconductor fin, wherein the first semiconductor layer comprises a quantum well layer including a smaller bandgap than a bandgap of the semiconductor fin, the SiGe having a Ge concentration of at least approximately 10%;
- a second semiconductor layer comprising tensile strained silicon directly wrapped around and on the first semiconductor layer, wherein the second semiconductor layer includes a smaller bandgap than the bandgap of the semiconductor fin and a larger bandgap than the bandgap of the first semiconductor layer;
- and
- a dielectric layer adjacent the second semiconductor layer;
- wherein the first semiconductor layer provides a quantum well for holes;
- and wherein the second semiconductor layer provides a quantum well for electrons.
6 more elements
Dependencies are inferred from the claim text.