Method for fabricating conducting structure and thin film transistor array panel

A method of providing a thin film transistor array panel, comprising:

• disposing a channel material layer over a substrate, the channel material layer comprising an oxide semiconductor material;
• disposing a lower sub-layer over a substrate, the lower sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and zinc content in the bottom sub-layer substantially defines a first indium to zinc content ratio;
• performing a first hydrogen treatment over an exposed surface of the lower sub-layer for introducing hydrogen content therein;
• disposing a middle sub-layer over the lower sub-layer, the middle sub-layer comprising a metal material;
• disposing an upper sub-layer over the middle sub-layer, the upper sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and the zinc content in the upper sub-layer substantially defines a second indium to zinc content ratio smaller than the first indium to zinc content ratio;
• and
• patterning the multi-layered conductive structure to generate a composite lateral etch profile.