FinFETs and methods for forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJeffrey Junhao Xu
Life of this patent
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Abstract
A FinFET includes a semiconductor fin including an inner region, and a germanium-doped layer on a top surface and sidewall surfaces of the inner region. The germanium-doped layer has a higher germanium concentration than the inner region. The FinFET further includes a gate dielectric over the germanium-doped layer, a gate electrode over the gate dielectric, a source region connected to a first end of the semiconductor fin, and a drain region connected to a second end of the semiconductor fin opposite the first end. Through the doping of germanium in the semiconductor fin, the threshold voltage may be tuned.
Claims20
A method comprising:
- recessing isolation regions, wherein a portion of a semiconductor strip between the isolation regions is over top surfaces of the recessed isolation regions, and forms a semiconductor fin;
- doping germanium into a middle portion of the semiconductor fin to form a germanium channel doping layer;
- forming a dummy gate to cover the middle portion of the semiconductor fin;
- forming an Inter-Layer Dielectric (ILD) to cover end portions of the semiconductor fin, wherein the end portions of the semiconductor fin are on opposite sides of the middle portion;
- removing the dummy gate to form a recess, wherein the middle portion is exposed to the recess;
- and
- forming a gate dielectric and a gate electrode in the recess and over the germanium channel doping layer, wherein the gate dielectric comprises a portion overlapping the germanium channel doping layer.
A method comprising:
- forming a semiconductor fin comprising:
- doping germanium into an outer portion of the semiconductor fin to form a germanium-doped layer on a top surface and sidewall surfaces of an inner region of the semiconductor fin, with the inner region of the semiconductor fin undoped with germanium when the germanium is doped into the outer portion of the semiconductor fin;
- forming a gate dielectric over the germanium-doped layer;
- forming a gate electrode over the gate dielectric;
- forming a source region connected to a first end of the semiconductor fin;
- and
- forming a drain region connected to a second end of the semiconductor fin opposite to the first end, wherein the source region and the drain region are substantially free from germanium.
A method comprising:
- recessing isolation regions, wherein a portion of a semiconductor strip between the isolation regions is higher than top surfaces of the recessed isolation regions, and forms a semiconductor fin;
- depositing a silicon germanium layer on a top surface and sidewalls of the semiconductor fin;
- performing a thermal oxidation on the silicon germanium layer to form a germanium-doped layer;
- removing a silicon oxide layer generated by the thermal oxidation to reveal the germanium-doped layer;
- forming a dummy gate to cover a middle portion of the germanium-doped layer;
- forming an Inter-Layer Dielectric (ILD) to cover end portions of the germanium-doped layer;
- removing the dummy gate to form a recess, wherein the middle portion is exposed to the recess;
- and
- forming a gate dielectric and a gate electrode in the recess and over the germanium-doped layer.
Dependencies are inferred from the claim text.