Power MOSFET device structure for high frequency applications

A method for manufacturing a power MOSFET device in a semiconductor substrate comprising:

• implanting a JFET (junction field effect transistor) region of a first conductivity type in an upper portion of the semiconductor substrate followed by growing a gate oxide layer on a top surface of the semiconductor substrate then depositing a gate layer on top of the gate oxide layer followed by applying a gate mask to etch and pattern the gate layer into a plurality of planar gates on the top surface of the semiconductor substrate wherein each of the planar gates is patterned into two split gate segments separated by a segment gap;
• implanting body regions of a second conductivity type in the upper portion of the semiconductor substrate with a top surface of the body region surrounding a bottom surface of the planar gate followed by applying a source mask to implant source regions encompassed by the body regions;
• depositing an inter-layer insulation layer covering over an entire top surface of the MOSFET device wherein the insulation layer forming a dip slot over each of the segment gaps separating the split gate segments wherein the dip slot vertically extending below a top surface of the split gate segments;
• and
• applying contact trench mask for opening a plurality of source contact trenches and opening a plurality of gate contact trenches through the inter-layer insulation layer followed by depositing a top metal layer and patterning the top metal layer into a source metal with the source metal filling the dip slots of the insulation layer formed between the split gate segments wherein the source metal filling the dip slots vertically extending below a top surface of the split gate segments.