Double-resurf LDMOS with drift and PSURF implants self-aligned to a stacked gate “bump” structure

A method of fabricating a double-RESURF LDMOS transistor on a semiconductor substrate, the method comprising:

• forming a deep N-well region in the semiconductor substrate, wherein a base oxide layer is disposed on an upper surface of the semiconductor substrate over a first portion of the deep N-well region;
• forming a mask on the upper surface such that the mask defines an opening that exposes a portion of the upper surface located over a second portion of the deep N-well region;
• forming an n-type drift implant region and a p-type surface field implant region in the semiconductor substrate by implanting associated n-type and p-type dopant materials through the opening defined in the mask;
• forming a gate dielectric structure on the exposed portion of the upper surface such that both the n-type drift implant region and the p-type surface field implant region are self-aligned to the gate dielectric structure;
• removing the mask;
• and
• forming a gate electrode on a portion of the base oxide layer and a portion of the gate dielectric structure.

A method of fabricating a double-RESURF LDMOS transistor, the method comprising:

• performing a first implant process during which an N-type dopant is implanted in a first region of a base semiconductor portion;
• performing a second implant process during which a P-type dopant is implanted in a second region of the base semiconductor substrate, the second region overlapping the first region;
• forming an epitaxial layer over the base portion, wherein a semiconductor substrate includes the base semiconductor portion and the epitaxial silicon layer, and an upper surface of the semiconductor substrate is formed by an exposed surface of the epitaxial layer;
• annealing the semiconductor substrate such that the P-type dopant and the N-type dopant diffuse into the epitaxial layer to form a P-type buried layer and an N-type buried layer, wherein the P-type buried layer is disposed over the N-type buried layer;
• forming a deep N-well region in a semiconductor substrate using a dopant having a first conductivity type, wherein the semiconductor substrate includes a base oxide layer disposed on an upper surface thereof and located over a first portion of the deep N-well region, and wherein the deep N-well region extends from the upper surface to the N-type buried layer;
• forming a n-type drift implant region, a p-type surface field implant region and a gate dielectric structure through an opening defined in a mask such that the n-type drift implant region and the p-type surface field implant region are formed inside a second portion of the well region, and such that the gate dielectric structure is disposed on the upper surface, wherein both the n-type drift implant region and the p-type surface field implant region are self-aligned to the gate dielectric structure;
• and
• forming a gate electrode on a portion of the base oxide layer and a portion of the gate dielectric structure.