US 9,806,170 B1 · Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI

Abstract

A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.

Claims7

Dependent claims

A method comprising:

providing p-type field effect transistor (PFET) core device (SG) and I/O device (EG) gate structures and n-type field effect transistor (NFET) SG and EG gate structures on a substrate, the PFET and NFET structures laterally separated;
forming a first conformal nitride layer over the substrate;
forming an oxide liner over the substrate;
forming a second conformal nitride layer on sidewalls of the PFET and NFET EG gate structures;
removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG gate structures and substrate;
forming raised source/drain (RSD) structures on opposite sides of each of the PFET SG and EG gate structures;
removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG gate structures and substrate;
and
forming RSD structures on opposite sides of each of the NFET SG and EG gate structures.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application

15/151,550Filed 11 May 2016

Published

US 2017/0330953 A116 Nov 2017

Granted

31 Oct 2017

Term ends

Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10D 64/021
Manufacture or treatment: using multiple gate spacer layers, e.g. bilayered sidewall spacers
H10D 30/0275
Of lateral single-gate IGFETs: forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised…
H10D 30/637
Insulated-gate field-effect transistors [IGFET]: lateral IGFETs having no inversion channels, e.g. buried channel lateral IGFETs, normally-on…
H10D 64/015
Manufacture or treatment: removing at least parts of gate spacers, e.g. disposable spacers

Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI

Life of this patent

Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI

Life of this patent

Abstract

Claims7