Semiconductor device having an nMOS SGT and a pMOS SGT

A semiconductor device comprising:

• a first fin-shaped layer including silicon on a substrate, wherein the first fin-shaped layer is a single-stage plateau extending in a first direction;
• a second fin-shaped layer including silicon on the substrate, wherein the second fin-shaped layer is a single-stage plateau extending in the first direction;
• a first insulating film around the first fin-shaped layer and the second fin-shaped layer;
• a first pillar-shaped layer including silicon on the first fin-shaped layer;
• a second pillar-shaped layer including silicon on the second fin-shaped layer, where a width of a bottom of the first pillar-shaped layer is equal to a width of a top of the first fin-shaped layer only in a width direction perpendicular to the first direction, and a width of a bottom of the second pillar-shaped layer is equal to a width of a top of the second fin-shaped layer only in the width direction;
• an n-type diffusion layer in an upper portion of the first fin-shaped layer and a lower portion of the first pillar-shaped layer;
• a p-type diffusion layer in an upper portion of the second fin-shaped layer and a lower portion of the second pillar-shaped layer;
• a gate insulating film around the first pillar-shaped layer;
• a first metal gate electrode around the gate insulating film;
• a gate insulating film around the second pillar-shaped layer;
• a second metal gate electrode around the gate insulating film;
• a metal gate line connected to the first metal gate electrode and to the second metal gate electrode and extending in a direction perpendicular to the first fin-shaped layer and the second fin-shaped layer.