Controlling channel length for vertical FETs

A method of fabricating a vertical-type semiconductor device, the method comprising:

• forming a semiconductor substrate including a first source/drain (S/D) region, and forming a channel region over the S/D region;
• forming a sacrificial etch-back control stack on an upper surface of the channel region, and forming a hardmask cap over the sacrificial etch-back control stack;
• depositing an electrically conductive gate layer that conforms to outer surfaces of the channel region, etch-back control stack, and hardmask cap;
• performing a first etching process comprising a first etching chemistry that recesses the electrically conductive gate layer at a first etching rate to form an initial gate defining a first gate length;
• removing the sacrificial etch-back control stack and hardmask cap to form a trench extending between inner sidewalls of the gate;
• performing a second etching process comprising the first etching chemistry, the second etching process applied to the initial gate via the trench such that a localized etching area defined by the trench reduces an etching rate of the second etching process and the initial gate is recessed to define a second gate length that is less than the first gate length;
• and
• forming a second S/D region on the upper surface of the channel region to form the vertical-type semiconductor device.