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US 9,806,147 B2Granted
Semiconductor device
AssigneeRenesas Electronics Corporation
InventorsKosuke Yoshida, Tetsuya Nitta, Atsushi Sakai
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Abstract
In a semiconductor device, a p+ back gate region (PBG) is arranged in a main surface (S1) between first and second portions (P1, P2) of an n+ source region (SR), and arranged on a side closer to an n+ drain region (DR) with respect to the n+ source region (SR). Thereby, a semiconductor device having a high on-state breakdown voltage can be obtained.
Claims14
A semiconductor device having a lateral insulated gate field effect transistor portion, comprising:
- a semiconductor substrate having a main surface and a trench formed in said main surface;
- a gate electrode of said insulated gate field effect transistor portion embedded within said trench in said semiconductor substrate;
- a first impurity region of a first conductivity type which has first and second portions separated from each other along said trench in said main surface, and serves as a source or an emitter;
- a second impurity region which is arranged in said main surface on a side of the first impurity region opposite to said trench, and serves as a drain of the first conductivity type or a collector of a second conductivity type;
- and
- a back gate region of the second conductivity type which is arranged in said main surface between said first and second portions of the first impurity region, and arranged between said second impurity region and said first and second portions of said first impurity region.
3 more elements
Dependencies are inferred from the claim text.