3DIC seal ring structure and methods of forming same

A method of forming a semiconductor device, the method comprising:

• providing a first substrate having one or more overlying first dielectric layers and a first conductive interconnect in the one or more first dielectric layers;
• providing a second substrate having one or more overlying second dielectric layers, a second conductive interconnect in the one or more second dielectric layers, and a first seal ring structure in the one or more second dielectric layers;
• bonding the first substrate to the second substrate, the first substrate being bonded to the second substrate such that a topmost dielectric layer of the first dielectric layers contacts a topmost dielectric layer of the second dielectric layers;
• forming a first conductive feature extending through the one or more first dielectric layers and the topmost dielectric layers of first and second dielectric layers to the second conductive interconnect in the one or more second dielectric layers, the first conductive feature having a first width in the one or more first dielectric layers;
• and
• forming a second seal ring structure extending through the one or more first dielectric layers and the topmost dielectric layers of first and second dielectric layers, the second seal ring structure having the first width in the one or more first dielectric layers, the second seal ring structure being electrically isolated from the first conductive feature.

A method comprising:

• bonding a first surface a first chip to a second surface of a second chip, the first chip having a substrate and a plurality of dielectric layers on a front side of the substrate, the substrate having a backside opposite the front side, the substrate having active devices in the front side in a first region, the substrate having an isolation region in the front side in a second region adjacent the first region, the isolation region extending from the front side of the substrate into the substrate, the plurality of dielectric layers having metallization layers formed therein;
• patterning the substrate, wherein the patterning the substrate exposes a first surface of the isolation region in the second region of the substrate, the first surface of the isolation region being parallel to a major surface of the substrate;
• forming a first conductive feature in the second region of the substrate, the first conductive feature extending from the isolation region of the first chip to a metallization layer in the second chip;
• and
• forming a first seal ring structure in the second region of the substrate, the first seal ring structure extending from the isolation region of the first chip to a second seal ring structure in the second chip.