Thin film transistor array substrate and manufacture method thereof

A thin film transistor array substrate, comprising a substrate having a surface and a first thin film transistor and a storage capacitor formed on the surface of the substrate;

• wherein the first thin film transistor comprises a first gate formed on the surface of the substrate and the storage capacitor comprises a first electrode plate formed on the surface of the substrate and spaced from the first gate by a predetermined distance along the surface of the substrate, a gate isolation layer formed on the surface of the substrate, the first gate, and the first electrode plate so as to cover the first gate and the first electrode plate such that the gate isolation layer comprises a raised portion located on first electrode plate by being raised above a top surface of the gate isolation layer around the first electrode plate;
• wherein the first thin film transistor further comprises a first oxide semiconductor layer formed on the gate isolation layer and located above and corresponding to the first gate;
• and
• wherein an etching stopper layer is formed on the gate isolation layer and the first oxide semiconductor layer and comprises a first part that covers the first oxide semiconductor layer and a second part that extends from the first part and the top surface of the gate isolation layer and covers the gate isolation layer, the first part of the etching stopper layer being formed with openings in which a first drain and a first source of the first thin film transistor are formed and in electrical connection with the first oxide semiconductor layer, the second part of the etching stopper layer being formed with an opening corresponding to and exposing a top of the raised portion of the gate isolation layer such that a top of the second part of the etching stopper layer is substantially flush with the top of the raised portion of the gate isolation layer, a second electrode plate of the storage capacitor being formed on and in direct contact with the exposed top of the raised portion of the gate isolation layer and corresponding to the first electrode plate.