High voltage three-dimensional devices having dielectric liners

An apparatus, comprising:

• a first transistor, comprising:
• a first semiconductor fin having a top portion, a first sidewall and a second sidewall, the first semiconductor fin comprising a semiconductor material;
• a first gate dielectric structure directly on the top portion and at least a portion of the first sidewalls and at least a portion of the second sidewall of the first semiconductor fin, the first gate dielectric structure comprising a first dielectric layer that conforms to the top portion of the first semiconductor fin and to at least the portion of both the first sidewall and the portion of second sidewall of the first semiconductor fin, and a second dielectric layer, the second dielectric layer conforming to a top portion of the first dielectric layer and to at least a portion of the first dielectric layer that conforms to the first sidewall of the first semiconductor fin and to at least a portion of the first dielectric layer that conforms to the second sidewall of the first semiconductor fin, the first gate dielectric structure having a first total thickness that is substantially the same at the top of the first semiconductor fin and at a first location adjacent the first sidewall of the first semiconductor fin and at a second location adjacent the second sidewall of the first semiconductor fin;
• a first gate electrode on the first gate dielectric structure, the first gate dielectric structure being between the first gate electrode and the top portion of the first semiconductor fin, at least a portion of the first sidewall of the first semiconductor fin, and at least a portion of the second sidewall of the first semiconductor fin;
• and
• a first source contact, the first source contact being separated from the first gate electrode by a first distance;
• and
• a second transistor, comprising:
• a second semiconductor fin having a top portion, a first sidewall and a second sidewall, the second semiconductor fin comprising a semiconductor material;
• a second gate dielectric structure directly on the top portion and at least a portion of the first sidewalls and at least a portion of the second sidewall of the second semiconductor fin, the second gate dielectric structure comprising a first dielectric layer that conforms to the top portion of the second semiconductor fin and to at least the portion of both the first sidewall and the portion of the second sidewall of the second semiconductor fin, the second gate dielectric structure having a second total thickness that is substantially the same at the top of the second semiconductor fin and at a first location adjacent the first sidewall of the second semiconductor fin and at a second location adjacent the second sidewall of the second semiconductor fin, the second total thickness being smaller than the first total thickness;
• a second gate electrode on the second gate dielectric structure, the second gate dielectric structure being between the second gate electrode and the top portion of the second semiconductor fin, at least a portion of the first sidewall of the second semiconductor fin, and at least a portion of the second sidewall of the second semiconductor fin;
• and
• a second source contact, the second source contact being separated from the second gate electrode by a second distance smaller than the first distance.