Non-uniform spacing in transistor stacks

A field-effect transistor stack comprising:

• a first field-effect transistor having a first plurality of source fingers, a first plurality of corresponding drain fingers, and a first plurality of gate fingers including a gate finger disposed between each adjacent pair of source and drain fingers of the first plurality of drain fingers and the first plurality of source fingers, each of the first plurality of gate fingers having a first gate width, a respective source finger and its corresponding adjacent drain finger of the first field-effect transistor being separated by a first drain-to-source distance, the first field-effect transistor representing an end stage of the field-effect transistor stack;
• a second field-effect transistor in a series connection with, and adjacent to the first field-effect transistor, the second field-effect transistor having a second plurality of source fingers, a second plurality of corresponding drain fingers, and a second plurality of gate fingers including a gate finger disposed between each adjacent pair of source and drain fingers of the second plurality of drain fingers and the second plurality of source fingers, each of the second plurality of gate fingers having a second gate width that is greater than the first gate width, a respective source finger and its corresponding adjacent drain finger of the second field-effect transistor being separated by a second drain-to-source distance that is greater than the first drain-to-source distance;
• and
• a third field-effect transistor in a series connection with, and adjacent to, the second field-effect transistor, the third field-effect transistor having a third plurality of source fingers, a third plurality of corresponding drain fingers, and a third plurality of gate fingers including a gate finger disposed between each adjacent pair of source and drain fingers of the third plurality of drain fingers and the third plurality of source fingers, each of the third plurality of gate fingers having a third gate width that is greater than the second gate width, a respective source finger and its corresponding adjacent drain finger of the third field-effect transistor being separated by a third drain-to-source distance that is greater than the second drain-to-source distance.

A transistor stack comprising:

• a plurality of field-effect transistors connected in series;
• a first field-effect transistor of the plurality of field-effect transistors having a first drain-to-source spacing and a first gate width, the first field-effect transistor representing an end stage of the transistor stack;
• a second field-effect transistor of the plurality of field-effect transistors connected in series with, and adjacent to, the first field-effect transistor, the second field-effect transistor having a second drain-to-source spacing that is greater than the first drain-to-source spacing and a second gate width that is greater than the first gate width;
• and
• a third field-effect transistor of the plurality of field-effect transistors connected in series with, and adjacent to, the second field-effect transistor, the third field-effect transistor having a third drain-to-source spacing that is greater than the second drain-to-source spacing and a third gate width that is greater than the second gate width.