US 9,806,092 B1Granted

Semiconductor memory device and methods for manufacturing the same

AssigneeToshiba Memory Corporation

InventorYoichi Minemura

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Abstract

According to one embodiment, a semiconductor memory device includes first to fourth conductive layers, a first intermediate insulating layer, a second intermediate insulating layer, an inter-layer insulating layer, a first semiconductor body, a first memory layer, a second semiconductor body, a second memory layer, and a first interconnect. The second conductive layer is separated from the first conductive layer in a first direction. The third conductive layer is arranged with the first conductive layer in a second direction crossing the first direction. The fourth conductive layer is separated from the third conductive layer in the first direction and arranged with the second conductive layer in the second direction. The first intermediate insulating layer is provided between the first conductive layer and the third conductive layer. The second intermediate insulating layer is provided between the second conductive layer and the fourth conductive layer.

Claims20

Dependent claims

A semiconductor memory device, comprising:

a first conductive layer;
a second conductive layer separated from the first conductive layer in a first direction;
a third conductive layer arranged with the first conductive layer in a second direction crossing the first direction;
a fourth conductive layer separated from the third conductive layer in the first direction and arranged with the second conductive layer in the second direction;
a first intermediate insulating layer provided between the first conductive layer and the third conductive layer;
a second intermediate insulating layer provided between the second conductive layer and the fourth conductive layer;
an inter-layer insulating layer including an intermediate partial region, the intermediate partial region being between the first intermediate insulating layer and the second intermediate insulating layer;
a first semiconductor body extending through the first conductive layer and the second conductive layer in the first direction;
a first memory layer provided between the first conductive layer and the first semiconductor body;
a second semiconductor body extending through the third conductive layer and the fourth conductive layer in the first direction;
a second memory layer provided between the third conductive layer and the second semiconductor body;
and
a first interconnect electrically connected to the first semiconductor body and the second semiconductor body,
at least one of the first intermediate insulating layer or the second intermediate insulating layer including a material different from a material of the intermediate partial region.

11 more elements

A method for manufacturing a semiconductor memory device, comprising:

forming a stacked film by alternately stacking a first film and a second film on a base semiconductor layer, the stacked film including a plurality of the first films and a plurality of the second films;
forming a first pillar-shaped structure body and a second pillar-shaped structure body, the first pillar-shaped structure body including a first semiconductor body and a first memory layer, the first semiconductor body extending through the stacked film along a stacking direction of the stacked film, the first memory layer being provided between the first semiconductor body and the stacked film, the second pillar-shaped structure body including a second semiconductor body and a second memory layer, the second semiconductor body extending through the stacked film along the stacking direction, the second memory layer being provided between the second semiconductor body and the stacked film;
forming a hole in the stacked film;
causing a third portion of the plurality of first films to remain while removing a first portion and a second portion of the plurality of first films via the hole, the third portion being positioned between the first pillar-shaped structure body and the second pillar-shaped structure body, the first portion being positioned between the third portion and the first pillar-shaped structure body, the second portion being positioned between the third portion and the second pillar-shaped structure body;
forming a plurality of conductive layers from a conductive material by introducing the conductive material to at least a portion of a space formed by the removing of the first portion and the second portion;
and
forming an interconnect electrically connected to the first semiconductor body and the second semiconductor body.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/461,590Filed 17 Mar 2017 · us provisional application
Priority: 12 Sep 2016
Granted: 31 Oct 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10B 43/10
EEPROM devices comprising charge-trapping gate insulators: characterised by the top-view layout
H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/50
EEPROM devices comprising charge-trapping gate insulators: characterised by the boundary region between the core and peripheral circuit regions
H10D 84/016
The components including insulated gates, e.g. IGFETs: the components including vertical IGFETs