Anti-fuse with reduced programming voltage
AssigneeInternational Business Machines Corporation
InventorsKangguo Cheng, Juntao Li, Chengwen Pei, Geng Wang
Life of this patent
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Abstract
A method for integrating transistors and anti-fuses on a device includes epitaxially growing a semiconductor layer on a substrate and masking a transistor region of the semiconductor layer. An oxide is formed on an anti-fuse region of the semiconductor layer. A semiconductor material is grown over the semiconductor layer to form an epitaxial semiconductor layer in the transistor region and a defective semiconductor layer in the anti-fuse region. Transistor devices in the transistor region and anti-fuse devices in the anti-fuse region are formed wherein the defective semiconductor layer is programmable by an applied field.
Claims14
A method for integrating transistors and anti-fuses on a device, comprising:
- epitaxially growing a semiconductor layer on a substrate;
- masking a transistor region of the semiconductor layer;
- forming an oxide on an anti-fuse region of the semiconductor layer;
- growing a semiconductor material over the semiconductor layer to form an epitaxial semiconductor layer in the transistor region and a defective semiconductor layer in the anti-fuse region;
- and
- forming transistor devices in the transistor region and anti-fuse devices in the anti-fuse region wherein the defective semiconductor layer is programmable by an applied field.
A method for integrating transistors and anti-fuses on a device, comprising:
- epitaxially growing a semiconductor layer on a substrate;
- masking a transistor region of the semiconductor layer with a pad dielectric layer;
- forming an oxide on an anti-fuse region of the semiconductor layer;
- removing the pad dielectric layer;
- growing a semiconductor material over the semiconductor layer to form a strained semiconductor layer in the transistor region and a defective semiconductor layer in the anti-fuse region;
- and
- forming transistor devices in the transistor region and anti-fuse devices in the anti-fuse region by:
- forming gate structures concurrently in the transistor region and the anti-fuse region;
- and
- forming source and drain regions adjacent to the gate structures in the transistor region and the anti-fuse region, wherein the defective semiconductor layer in the anti-fuse region is programmable by an applied field.
Dependencies are inferred from the claim text.