US 9,806,083 B2Granted

Static random access memory (SRAM) bit cells with wordlines on separate metal layers for increased performance, and related methods

AssigneeQUALCOMM Incorporated

InventorsNiladri Narayan Mojumder, Stanley Seungchul Song, Zhongze Wang, Kern Rim, Choh Fei Yeap

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Abstract

Static random access memory (SRAM) bit cells with wordlines on separate metal layers for increased performance are disclosed. In one aspect, an SRAM bit cell is disclosed employing a write wordline in a second metal layer, a first read wordline in a third metal layer, and a second read wordline in a fourth metal layer. Employing wordlines in separate metal layers allows wordlines to have increased widths, which decrease wordline resistance, decrease access time, and increase performance of the SRAM bit cell. To employ wordlines in separate metal layers, multiple tracks in a first metal layer are employed. To couple read wordlines to the tracks to communicate with SRAM bit cell transistors, landing pads are disposed on corresponding tracks disposed in the first metal layer. Landing pads corresponding to the write wordline are placed on corresponding tracks disposed in the first metal layer.

Claims28

Dependent claims

A static random access memory (SRAM) bit cell comprising:

a plurality of tracks employed in a first metal layer;
a write wordline employed in a second metal layer different from the first metal layer;
a first read wordline employed in a third metal layer different from the first metal layer and the second metal layer;
a second read wordline employed in a fourth metal layer different from the first metal layer, the second metal layer, and the third metal layer;
each first read wordline landing pad of a plurality of first read wordline landing pads disposed on a corresponding track of the plurality of tracks, wherein:
each first read wordline landing pad is physically and directly coupled to the corresponding track;
and
each first read wordline landing pad electrically couples the first read wordline and the corresponding track;
each second read wordline landing pad of a plurality of second read wordline landing pads disposed on a corresponding track of the plurality of tracks, wherein:
each second read wordline landing pad is physically and directly coupled to the corresponding track;
and
each second read wordline landing pad electrically couples the second read wordline and the corresponding track;
and
each write wordline landing pad of a plurality of write wordline landing pads disposed on a corresponding track of the plurality of tracks, wherein:
each write wordline landing pad is physically and directly coupled to the corresponding track;
and
each write wordline landing pad electrically couples the write wordline and the corresponding track.

14 more elements

A static random access memory (SRAM) bit cell comprising:

a means for disposing a plurality of tracks employed in a first metal layer;
a means for disposing a write wordline employed in a second metal layer different from the first metal layer;
a means for disposing a first read wordline employed in a third metal layer different from the first metal layer and the second metal layer;
a means for disposing a second read wordline employed in a fourth metal layer different from the first metal layer, the second metal layer, and the third metal layer;
a means for disposing each first read wordline landing pad of a plurality of first read wordline landing pads on a corresponding track of the plurality of tracks, wherein:
each first read wordline landing pad is physically and directly coupled to the corresponding track;
and
each first read wordline landing pad electrically couples the first read wordline and the corresponding track;
a means for disposing each second read wordline landing pad of a plurality of second read wordline landing pads on a corresponding track of the plurality of tracks, wherein:
each second read wordline landing pad is physically and directly coupled to the corresponding track;
and
each second read wordline landing pad electrically couples the second read wordline and the corresponding track;
and
a means for disposing each write wordline landing pad of a plurality of write wordline landing pads on a corresponding track of the plurality of tracks, wherein:
each write wordline landing pad is physically and directly coupled to the corresponding track;
and
each write wordline landing pad electrically couples the write wordline and the corresponding track.

14 more elements

A method of fabricating a static random access memory (SRAM) bit cell comprising:

disposing a plurality of tracks employed in a first metal layer;
disposing a write wordline employed in a second metal layer different from the first metal layer;
disposing a first read wordline employed in a third metal layer different from the first metal layer and the second metal layer;
disposing a second read wordline employed in a fourth metal layer different from the first metal layer, the second metal layer, and the third metal layer;
disposing each first read wordline landing pad of a plurality of first read wordline landing pads on a corresponding track of the plurality of tracks, wherein:
each first read wordline landing pad is physically and directly coupled to the corresponding track;
and
each first read wordline landing pad electrically couples the first read wordline and the corresponding track;
disposing each second read wordline landing pad of a plurality of second read wordline landing pads on a corresponding track of the plurality of tracks, wherein:
each second read wordline landing pad is physically and directly coupled to the corresponding track;
and
each second read wordline landing pad electrically couples the second read wordline and the corresponding track;
and
disposing each write wordline landing pad of a plurality of write wordline landing pads on a corresponding track of the plurality of tracks, wherein:
each write wordline landing pad is physically and directly coupled to the corresponding track;
and
each write wordline landing pad electrically couples the write wordline and the corresponding track.

14 more elements

A static random access memory (SRAM), comprising:

an SRAM array, comprising a plurality of SRAM bit cells;
each SRAM bit cell of the plurality of SRAM bit cells comprises:
a plurality of tracks employed in a first metal layer;
a write wordline employed in a second metal layer different from the first metal layer;
a first read wordline employed in a third metal layer different from the first metal layer and the second metal layer;
a second read wordline employed in a fourth metal layer different from the first metal layer, the second metal layer, and the third metal layer;
each first read wordline landing pad of a plurality of first read wordline landing pads disposed on a corresponding track of the plurality of tracks, wherein:
each first read wordline landing pad is physically and directly coupled to the corresponding track;
and
each first read wordline landing pad electrically couples the first read wordline and the corresponding track;
each second read wordline landing pad of a plurality of second read wordline landing pads disposed on a corresponding track of the plurality of tracks, wherein:
each second read wordline landing pad is physically and directly coupled to the corresponding track;
and
each second read wordline landing pad electrically couples the second read wordline and the corresponding track;
and
each write wordline landing pad of a plurality of write wordline landing pads disposed on a corresponding track of the plurality of tracks wherein:
each write wordline landing pad is physically and directly coupled to the corresponding track;
and
each write wordline landing pad electrically couples the write wordline and the corresponding track.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/559,205Filed 3 Dec 2014
Published: US 2016/0163713 A19 Jun 2016
Granted: 31 Oct 2017
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10B 10/00
Static random access memory [sram] devices
G11C 5/063
Arrangements for interconnecting storage elements electrically, e.g. by wiring: voltage and signal distribution in integrated semi-conductor…
G11C 8/14
Arrangements for selecting an address in a digital store: word line organisation; Word line lay-out
G11C 8/16
Arrangements for selecting an address in a digital store: multiple access memory array, e.g. addressing one storage element via at least two…