Integrated circuit devices having a Fin-type active region and methods of manufacturing the same

An integrated circuit device comprising:

• a substrate including first and second fin-type active regions;
• a first gate structure on the first fin-type active region, the first gate structure including:
• a first gate insulating layer on an upper surface and both side surfaces of the first fin-type active region;
• a first gate electrode on the first gate insulating layer;
• and
• a second gate electrode on the first gate electrode;
• and
• a second gate structure on the second fin-type active region, the second gate structure including:
• a second gate insulating layer on an upper surface and both side surfaces of the second fin-type active region;
• a third gate insulating layer on the second gate insulating layer;
• a third gate electrode on the third gate insulating layer;
• and
• a fourth gate electrode on the third gate electrode,
• wherein a material of the first gate insulating layer is substantially different from a material of the third gate insulating layer.

An integrated circuit device comprising:

• a substrate including first and second fin-type active regions;
• a first gate structure on the first fin-type active region, the first gate structure including:
• a first gate insulating layer covering an upper surface and both side surfaces of the first fin-type active region;
• and
• a first gate electrode on the first gate insulating layer and having a first thickness in a first direction perpendicular to an upper surface of the substrate;
• and
• a second gate structure on the second fin-type active region, the second gate structure including:
• a second gate insulating layer covering an upper surface and both side surfaces of the second fin-type active region;
• a third gate insulating layer covering the upper surface and both side surfaces of the second fin-type active region, with the second gate insulating layer disposed therebetween;
• and
• a third gate electrode on the third gate insulating layer and having a second thickness that is different from the first thickness in the first direction,
• wherein a material of the first gate insulating layer is substantially different from a material of the third gate insulating layer.