Semiconductor device layout, memory device layout, and method of manufacturing semiconductor device

A layout of a memory device, the layout stored on a non-transitory computer-readable medium and comprising:

• a plurality of memory cells, each memory cell of the plurality of memory cells comprising first and second portions, each portion of the first and second portions comprising:
• a first transistor coupled between a first power supply node and a storage node;
• a second transistor coupled between a second power supply node and the storage node;
• a third transistor coupled between a bitline node and the storage node;
• a first contact patterning region covering active area regions, gate electrodes and spacers of the first, second and third transistors, the first contact patterning region covering less than an entirety of the each portion;
• and
• a second contact patterning region overlapping the first contact patterning region, the second contact patterning region being between the first power supply node and the second power supply node.

A layout of a semiconductor device, the layout stored on a non-transitory computer-readable medium and comprising:

• a first active area region;
• a second active area region;
• a first gate electrode crossing the first active area region and the second active area region;
• a second gate electrode crossing the first active area region and the second active area region;
• a first spacer along a side of the first gate electrode;
• a second spacer along a side of the second gate electrode;
• a first contact patterning region overlapping the first active area region, the second active area region, the first gate electrode, the second gate electrode, the first spacer, and the second spacer;
• a second contact patterning region overlapping a portion of the first contact patterning region;
• a first contact area overlapping the first active area region;
• and
• a second contact area overlapping the second active area region,
• wherein each of the first contact area and the second contact area has a boundary defined by boundaries of the first contact patterning region, the second contact patterning region, the first spacer, and the second spacer.