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US 9,806,066 B2Granted
Semiconductor package including exposed connecting stubs
AssigneeSamsung Electronics Co., Ltd.
InventorMaohua Du
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes a substrate comprising a chip area and a peripheral area, at least one semiconductor chip mounted on the chip area, a plurality of stubs respectively on a plurality of pads arranged in the peripheral area, and a molding unit configured to cover at least a partial area of the at least one semiconductor chip and at least a partial area of the plurality of stubs on the substrate while exposing an upper surface of at least one of the plurality of stubs to outside of the molding unit, wherein at least a partial area of the upper surface of at least one of the plurality of stubs is substantially flat.
Claims18
A semiconductor package comprising:
- a substrate including a chip area and a peripheral area;
- at least one semiconductor chip on the chip area;
- a plurality of stubs on a plurality of pads respectively in the peripheral area;
- and
- a molding unit configured to cover at least a partial area of the at least one semiconductor chip and at least a partial area of the plurality of stubs on the substrate, the molding unit exposing an upper surface of at least one of the plurality of stubs to an outside of the molding unit,
- a first bonding wire configured to connect the at least one semiconductor chip and the plurality of pads on the substrate;
- and
- a second bonding wire configured to connect the at least one semiconductor chip and the plurality of stubs,
- wherein at least a partial area of the upper surface of at least one of the plurality of stubs is substantially flat;
- wherein at least one of the plurality of stubs comprises a plurality of sub-stubs stacked in a first direction perpendicular to an upper surface of the substrate and each of the plurality of sub-stubs has a middle width greater than widths of an upper end and a lower end thereof;
- and
- wherein one end of the second bonding wire is connected to the at least one semiconductor chip and the other end thereof is between the plurality of sub-stubs and is connected to at least one of the plurality of stubs.
9 more elements
A semiconductor package comprising:
- a first package;
- and
- a second package on the first package,
- wherein the first package includes:
- a first substrate;
- at least one first semiconductor chip on the first substrate;
- a plurality of stubs on a plurality of pads respectively on the first substrate;
- and
- a first molding unit configured to cover at least a partial area of the at least one first semiconductor chip and at least a partial area of the plurality of stubs on the first substrate,
- at least one of the plurality of stubs comprising a plurality of sub-stubs stacked in a first direction perpendicular to an upper surface of the substrate, each of the plurality of sub-stubs having a middle width greater than widths of an upper end and a lower end thereof;
- at least a partial area of an upper surface of at least one of the plurality of stubs being substantially flat;
- a first bonding wire configured to connect the at least one first semiconductor chip and the plurality of pads on the first substrate;
- and
- a second bonding wire configured to connect the at least one first semiconductor chip and the plurality of stubs,
- wherein one end of the second bonding wire is connected to the at least one first semiconductor chip and the other end thereof is between the plurality of sub-stubs and is connected to at least one of the plurality of stubs;
- and
- wherein the second package includes:
- a second substrate;
- at least one second semiconductor chip on the second substrate;
- a second molding unit configured to cover at least a partial area of the at least one second semiconductor chip on the second substrate;
- and
- a plurality of external connection members on a lower surface of the second substrate,
- wherein the plurality of external connection members are respectively connected to the plurality of stubs.
20 more elements
A semiconductor package, comprising:
- at least one semiconductor chip and a plurality of stubs on a substrate, the plurality of stubs on a plurality of pads respectively;
- and
- a molding unit covering the at least one semiconductor chip and the plurality of stubs, the molding unit exposing a surface of at least one of the plurality of stubs that is opposite to the substrate;
- the plurality of stubs being configured to connect the substrate to an external device;
- and
- at least one of the plurality of stubs comprising a plurality of sub-stubs stacked in a first direction perpendicular to an upper surface of the substrate, each of the plurality of sub-stubs having a middle width greater than widths of an upper end and a lower end thereof,
- a first bonding wire configured to connect the at least one semiconductor chip and the plurality of pads on the substrate;
- and
- a second bonding wire configured to connect the at least one semiconductor chip and the plurality of stubs, and
- wherein one end of the second bonding wire is connected to the at least one semiconductor chip and the other end thereof is between the plurality of sub-stubs and is connected to at least one of the plurality of stubs.
7 more elements
Dependencies are inferred from the claim text.