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US 9,806,064 B2Granted
Package with multiple plane I/O structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHung-Chang Yu, Kai-Chun Lin, Yue-Der Chih
Life of this patent
Estimating the term…
Abstract
A embodiment package includes a three dimensional integrated circuit (3D IC) with first input/output pads on a first side and second input/output pads on a second side, a first fan out structure electrically coupled to the first input/output pads on the first side of the three dimensional integrated circuit, and a second fan out structure electrically coupled to the second input/output pads on the second side of the three dimensional integrated circuit.
Claims20
A method of forming a package, the method comprising:
- bonding one or more dies forming a chip stack, the chip stack having a first outermost die and a second outermost die opposite the first outermost die, the first outermost die being electrically coupled to the second outermost die;
- after forming the chip stack, bonding a first set of input/output pads of the first outermost die to a first side of a first substrate using a first set of connectors, a second side of the first substrate having second set of connectors;
- and
- bonding a second set of input/output pads of the second outermost die to a first side of a second substrate using a third set of connectors, a second side of the second substrate having a fourth set of connectors, wherein a pitch of the first set of connectors is different from a pitch of the third set of connectors, wherein the first substrate is electrically coupled to the second substrate only through the first set of connectors, the third set of connectors, and the chip stack.
1 more element
A method of forming a package, the method comprising:
- bonding a first side of a chip stack to a first side of a first substrate, the first side of the chip stack having a first set of contact pads, a second side of the first substrate having a first set of connectors, the second side of the first substrate being opposite the first side of the first substrate, wherein the chip stack comprises a plurality of chips bonded to each other, and wherein adjacent ones of the plurality of chips are electrically coupled before bonding the chip stack to the first side of the first substrate;
- and
- after bonding the first side of the chip stack to the first side of the first substrate, bonding a second side of the chip stack to a first side of a second substrate, the second side of the chip stack being opposite the first side of the chip stack, the second side of the chip stack having a second set of contact pads, a second side of the second substrate having a second set of connectors, the second side of the second substrate being opposite the first side of the second substrate, the first side of the first substrate facing the first side of the second substrate, a pitch of the first set of connectors being different from a pitch of the second set of connectors, a pitch of the first set of contact pads being different from a pitch of the second set of contact pads, the chip stack being interposed between the first substrate and the second substrate, the first substrate being electrically coupled to the second substrate only through a single electrical path comprising the chip stack.
A package comprising:
- a first substrate, the first substrate having a first side and a second side, the first side of the first substrate being opposite the second side of the first substrate, the second side of the first substrate having a first set of connectors;
- a second substrate, the second substrate having a first side and a second side, the first side of the second substrate being opposite the second side of the second substrate, the second side of the second substrate having a second set of connectors, wherein a pitch of the first set of connectors is different from a pitch of the second set of connectors;
- and
- a chip stack interposed between the first substrate and the second substrate, a first side of the chip stack having a first set of conductive features and a second side of the chip stack having a second set of conductive features, the first set of conductive features being coupled to the first side of the first substrate using a third set of connectors, the second set of conductive features being coupled to the first side of the second substrate using a fourth set of connectors, wherein a pitch of the third set of connectors is different from a pitch of the fourth set of connectors, wherein the chip stack comprises a plurality of chips bonded to each other, wherein adjacent ones of the plurality of chips are directly electrically coupled, and wherein the first substrate is electrically coupled to the second substrate only through the third set of connectors, the fourth set of connectors, and the chip stack.
1 more element
Dependencies are inferred from the claim text.