Semiconductor memory device

A semiconductor memory device comprising:

• a semiconductor substrate including a trench that defines first, second and third active patterns spaced apart from each other,
• each of the first, second and third active patterns having a long axis parallel to a first direction that is perpendicular to a second direction,
• each of the first, second, and third active patterns including first and second dopant regions,
• the first and second active patterns arranged to be spaced apart from each other in the second direction,
• the third active pattern arranged to be spaced apart from the first and second active patterns in a direction diagonal to the first and second directions;
• a device isolation layer in the trench, the device isolation layer exposing the first, second, and third active patterns;
• a first word line extending in the second direction, the first word line intersecting the first and second active patterns, the first and second dopant regions in each of the first and second active patterns being at both sides of the first word line respectively;
• a second word line extending in the second direction, the second word line intersecting the third active pattern, the first and second dopant regions formed in the third active pattern being at both sides of the second word line;
• a bit line extending in the first direction between the first active pattern and the third active pattern when viewed from a plan view, the bit line being connected to the first dopant regions of the first and third active patterns;
• and
• a source line extending in the first direction between the second active pattern and the third active pattern when viewed from the plan view, the source line being connected to the second dopant regions of the second and third active patterns.