Selective and non-selective barrier layer wet removal

A semiconductor device, comprising:

• a dielectric layer on a substrate;
• an opening in the dielectric layer;
• a first interconnect structure partially filling the opening in the dielectric layer, wherein the first interconnect structure comprises:
• a first barrier layer lining a bottom of the opening and sides of the opening up to a predetermined height below a top of the opening;
• and
• a first contact layer on the first barrier layer in the opening, wherein the first contact layer fills the opening to the predetermined height below the top of the opening;
• and
• a second interconnect structure on the first interconnect structure, wherein at least part of the second interconnect structure is in the opening, and includes a second contact layer on a second barrier layer;
• wherein the second contact layer fills the opening to the top of the opening.

A semiconductor device, comprising:

• a dielectric layer on a substrate;
• an opening in the dielectric layer;
• a first interconnect structure partially filling the opening in the dielectric layer, wherein the first interconnect structure comprises:
• a first barrier layer lining a bottom of the opening and sides of the opening up to a predetermined height below a top of the opening;
• and
• a first contact layer on the first barrier layer in the opening, wherein the first contact layer fills the opening to the predetermined height below the top of the opening;
• and
• a second interconnect structure on the first interconnect structure, wherein at least part of the second interconnect structure is in the opening, and includes a second contact layer on a second barrier layer;
• wherein the second barrier layer is on a top surface of the dielectric layer.

A semiconductor device, further comprising:

• a dielectric layer on a substrate;
• an opening in the dielectric layer;
• a first interconnect structure partially filling the opening in the dielectric layer, wherein the first interconnect structure comprises:
• a first barrier layer lining a bottom of the opening and sides of the opening up to a predetermined height below a top of the opening;
• and
• a first contact layer on the first barrier layer in the opening, wherein the first contact layer fills the opening to the predetermined height below the top of the opening;
• a second interconnect structure on the first interconnect structure, wherein at least part of the second interconnect structure is in the opening, and includes a second contact layer on a second barrier layer;
• an additional opening in the dielectric layer;
• a third interconnect structure partially filling the additional opening in the dielectric layer, wherein the third interconnect structure comprises:
• a third barrier layer lining a bottom of the additional opening and sides of the additional opening up to a predetermined height below a top of the additional opening;
• and
• a third contact layer on the third barrier layer in the opening, wherein the third contact layer fills the opening to the predetermined height below the top of the additional opening.

A semiconductor device, comprising:

• a dielectric layer on a substrate;
• a plurality of openings in the dielectric layer;
• a first interconnect structure partially filling the plurality of openings in the dielectric layer, wherein the first interconnect structure comprises:
• a first barrier layer lining a bottom and sides of each of the plurality of openings up to a predetermined height below a top of each of the plurality of openings;
• and
• a first contact layer on the first barrier layer in of each of the plurality of openings, wherein the first contact layer fills each of the plurality of openings to the predetermined height below the top of each of the plurality of openings;
• a second interconnect structure on the first interconnect structure in a first opening of the plurality of openings, wherein at least part of the second interconnect structure is in the first opening of the plurality of openings, and includes a second contact layer on a second barrier layer;
• and
• a dielectric cap layer on the first interconnect structure in a second opening of the plurality of openings, wherein at least part of the dielectric cap layer is in the second opening, and lines sides of a portion of the second opening from a top of the second opening to the first barrier layer in the second opening.

A semiconductor device, comprising:

• a dielectric layer on a substrate;
• an opening in the dielectric layer;
• an interconnect structure partially filling the opening in the dielectric layer, wherein the interconnect structure comprises:
• a barrier layer lining a bottom of the opening and sides of the opening up to a predetermined height below a top of the opening;
• and
• a contact layer on the first barrier layer in the opening, wherein the contact layer fills the opening to the predetermined height below the top of the opening;
• a dielectric cap layer on the interconnect structure in the opening, wherein at least part of the dielectric cap layer is in the opening, and lines sides of a portion of the opening from the top of the opening to the barrier layer;
• and
• an additional dielectric layer on the dielectric cap layer and filling the opening to at least the top of the opening.