Integrated circuit with power saving feature
AssigneeNXP USA, Inc.
InventorsAnis M. Jarrar, David R. Tipple, Jeff L. Warner
Life of this patent
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Abstract
An integrated circuit includes a first transistor including a first current electrode, a second current electrode, and a bulk tie; a first conductive line coupled between the first current electrode and a first supply voltage; and a second conductive line coupled to the second current electrode. A resistance of the second conductive line is at least 5 percent greater than a resistance of the first conductive line. The bulk tie is coupled to a second supply voltage. The first supply voltage is different than the second supply voltage.
Claims13
An integrated circuit, comprising:
- a first transistor including a first current electrode, a second current electrode, and a bulk tie;
- a second transistor including a first current electrode, a second current electrode, and a bulk tie, the second current electrode of the first transistor is connected to the first current electrode of the second transistor;
- a first conductive line coupled between the first current electrode of the first transistor and a first supply voltage;
- and
- a second conductive line coupled to the second current electrode of the second transistor and a second supply voltage, wherein a resistance of the second conductive line is at least 5 percent greater than a resistance of the first conductive line, wherein
- the bulk tie of the first transistor is coupled to the first supply voltage, the bulk tie of the second transistor is coupled to a third supply voltage, the third supply voltage is different than the first and second supply voltage, and the first supply voltage is different than the second supply voltage.
An integrated circuit, comprising:
- a P-channel metal oxide semiconductor (PMOS) transistor including a source electrode, a drain electrode and a bulk tie;
- an N-channel metal oxide semiconductor (NMOS) transistor including a source electrode, a drain electrode and a bulk tie;
- a first conductive line coupled to the source electrode of the PMOS transistor;
- a second conductive line coupled between the source electrode of the NMOS transistor and a second supply voltage;
- a third conductive line coupled between the drain electrode of the PMOS transistor and the drain electrode of the NMOS transistor, wherein
- a resistance of the second conductive line is at least 5 percent greater than a resistance of the first conductive line, and
- the bulk tie of the PMOS transistor is coupled to a first supply voltage, the bulk tie of the NMOS transistor is coupled to a third supply voltage, the third supply voltage is different than the first and second supply voltage, and the first supply voltage is different than the second supply voltage.
Dependencies are inferred from the claim text.