FDSOI voltage reference
AssigneeGlobalfoundries Inc.
InventorsAndres Bryant, Edward J. Nowak, Robert R. Robison
Life of this patent
Estimating the term…
Abstract
An integrated circuit having a reference device and method of forming the same. A reference device is disclosed having: a fully depleted n-type MOSFET implemented as a long channel device having a substantially undoped body; and a fully depleted p-type MOSFET implemented with as a long channel device having a substantially undoped body; wherein the n-type MOSFET and p-type MOSFET are connected in series and employ identical gate stacks, wherein each has a gate electrically coupled to a respective drain to form two diodes, and wherein both diodes are in one of an on state and an off state according to a value of an electrical potential applied across the n-type MOSFET and p-type MOSFET.
Claims20
A reference device, comprising:
- a fully depleted n-type metal oxide-silicon field effect transistor (MOSFET) implemented as a long channel device having a substantially undoped body;
- and
- a fully depleted p-type MOSFET implemented with as a long channel device having a substantially undoped body;
- wherein the n-type MOSFET and p-type MOSFET are connected in series and employ identical gate stacks, wherein each MOSFET has a gate electrically coupled to a respective drain thereof to form two diodes, and wherein both diodes are in one of an on state and an off state according to a polarity of an electrical potential applied across the n-type MOSFET and p-type MOSFET.
An integrated circuit (IC) having a reference device, comprising:
- a fully depleted n-type metal oxide-silicon field effect transistor (MOSFET) implemented as a long channel device having a substantially undoped body;
- and
- a fully depleted p-type MOSFET implemented as a long channel device having a substantially undoped body;
- wherein the n-type MOSFET and p-type MOSFET are connected in series and employ identical gate stacks, wherein each has a gate electrically coupled to a drain thereof, and both are in one of an on state and an off state according to a polarity of an electrical potential applied across the n-type MOSFET and p-type MOSFET.
A method of forming a reference circuit, comprising:
- forming a fully depleted n-type metal oxide-silicon field effect transistor (MOSFET) and a fully depleted p-type MOSFET adjacent each other, wherein both MOSFETs are implemented as long channel devices having substantially undoped bodies, and wherein each has a commonly formed gate stack;
- and
- wiring the n-type MOSFET and p-type MOSFET in series in which each has a gate electrically coupled to a drain thereof and both can be placed in one of an on state and an off state according to a polarity of an electrical potential applied across the n-type MOSFET and p-type MOSFET.
Dependencies are inferred from the claim text.