Back to results
US 9,805,955 B1Granted
Semiconductor package with multiple molding routing layers and a method of manufacturing the same
AssigneeUTAC Headquarters Pte. Ltd.
InventorsSaravuth Sirinorakul, Suebphong Yenrudee
Life of this patent
Estimating the term…
Abstract
Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package.
Claims15
A semiconductor package comprising:
- package terminals;
- a copper leadframe routing layer including copper routing circuits that are etched from a copper leadframe;
- at least one conductive ink printed routing layer, wherein each of the at least one conductive ink printed routing layer includes:
- a plurality of interconnections coupled with routing circuits associated with a previous routing layer that is directly beneath a current conductive ink printed routing layer;
- an intermediary insulation layer formed on top of the previous routing layer, wherein the plurality of interconnections protrudes from a top surface of the intermediary insulation layer that has an unnatural surface roughness that is rougher than the natural surface roughness of the intermediary insulation layer;
- and
- conductive ink routing circuits adhered on the unnaturally roughened top surface of the intermediary insulation layer;
- a die coupled with a topmost conductive ink printed routing layer;
- a topmost insulation layer encapsulating the die and the topmost conductive ink routing layer;
- and
- a bottommost insulation layer encapsulating the copper routing circuits.
8 more elements
A semiconductor package comprising:
- package terminals;
- a copper leadframe routing layer including copper routing circuits that are etched from a copper leadframe;
- at least one conductive ink printed routing layer, wherein each of the at least one conductive ink printed routing layer includes:
- a plurality of interconnections coupled with routing circuits associated with a previous routing layer that is directly beneath a current conductive ink printed routing layer;
- an intermediary insulation layer formed on top of the previous routing layer, wherein the plurality of interconnections protrudes from a top surface of the intermediary insulation layer that has an unnatural surface roughness that is rougher than the natural surface roughness of the intermediary insulation layer;
- and
- conductive ink routing circuits adhered on the unnaturally roughened top surface of the intermediary insulation layer, wherein each of the conductive ink routing circuits includes a plurality of conductive ink printed layers and a plurality of seed printed layers;
- a die coupled with a topmost conductive ink printed routing layer;
- a topmost insulation layer encapsulating the die and the topmost conductive ink routing layer;
- and
- a bottommost insulation layer encapsulating the copper routing circuits.
8 more elements
Dependencies are inferred from the claim text.