Bottom source/drain silicidation for vertical field-effect transistor (FET)

A method for manufacturing a semiconductor device, comprising:

• forming a first active region on a semiconductor substrate;
• forming a semiconductor layer on the first active region;
• patterning the semiconductor layer into a plurality of fins extending from the first active region vertically with respect to the semiconductor substrate, wherein the first active region is located under bottom ends of the plurality of fins;
• forming a silicide layer on exposed portions of the first active region;
• forming an electrically conductive contact on the silicide layer;
• forming a second active region on top ends of each of the plurality of fins;
• forming a gate structure between the plurality of fins, wherein the gate structure is positioned over the first active region and under the second active region;
• and
• forming a spacer layer on the silicide layer, wherein the electrically conductive contact extends through an opening in the spacer layer to contact the silicide layer;
• wherein the semiconductor device comprises a vertical field-effect transistor (FET) device configured to carry current through the plurality of fins in a direction perpendicular to a top surface of the semiconductor substrate on which the first active region is formed and from which the plurality fins vertically extend.